JP2824708B2 - Graphic drawing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic drawing apparatus for drawing a graphic in units of dots, and more particularly to an apparatus for improving the thickness of characters and figures.

[0002]

2. Description of the Related Art A figure drawing apparatus is incorporated in a word processor, a computer, or the like, and displays or prints characters and figures on a screen in response to a predetermined operation.

When a certain sentence is created, a method of thickening a character or a figure as shown in FIG. 7 is used to add rich expressive power to the sentence.

In FIG. 7, hatched circles are dots of a figure to be thickened, and white circles are dots added for thickening.

A figure drawn on a dot matrix is usually a line segment or a curve such as a circle or an ellipse. In addition, there are combinations of lines and curves, characters, and the like.

[0006]

When the figure is a line segment or a circle, it is easy to increase the line width of the figure. However, when the figure is an ellipse or a figure in which a straight line and a curve are combined, it is extremely difficult. Complicated.

As a simple method of increasing the line width of a figure, it is conceivable to draw a filled circle centered on, for example, an elliptical dot as shown in FIG. However, this method can be used when a figure is created as a basic pattern from the beginning, that is, when a dot is drawn. Not applicable when making Also, when the radius of the circle used for filling is small, the number of drawn dots is not large, but when the radius is large, it is necessary to draw many dots, and it is necessary to draw overlapping. More parts. Therefore, it takes a long time to draw. In addition,
Although it is possible to perform the processing in software,
The problem that processing with software generally takes a long time
There is.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a graphic drawing apparatus capable of processing line width expansion of an existing graphic at a high speed.

[0009]

According to a first aspect of the present invention, there is provided a first timing signal and a first timing signal.
The second timing signal having a frequency equal to or higher than the frequency of the
And a dot counter for each
A first memory and a second memory capable of storing
Each address of the first memory in response to the timing signal;
A first address generation circuit for sequentially designating
Address from the address generation circuit and the second timing
Generating a first address of a second memory in response to a signal;
Addresses adjacent to the address specified by the circuit in the specified order
And a second address generating circuit for selecting and outputting in the order
An image drawing device. The second memory is a second timing
Read from the address of the first memory in response to the
Only data of a predetermined value out of the data to be
To the address generated by the source generation circuit. The image of the present invention
The image drawing apparatus further stores the data stored in the second memory.
Means for giving a predetermined value to the first memory
It is characterized by the following.

[0010] In a second aspect, a plurality of first shifts are provided.
Register, a plurality of second shift registers, and each first shift register.
An address generation circuit for sequentially designating shift registers;
Generation of an address generation circuit in the first shift register
The shift register specified by the address
Each output buffer sequentially reading the data from the front and rear of the shift register in the shift register, performs a predetermined logic operation by relative output data of the output buffer,
An OR circuit that outputs data after the logical operation.
Generation of an address generation circuit for a second shift register of numbers
The shift register corresponding to the address to be
Graphic drawing device characterized by sequentially storing the output of
is there.

According to a third aspect of the present invention, each of the input terminal and the input terminal
A plurality of shift registers having an output end;
Address generation circuit for sequentially specifying the
Address, the address generated by the address generation circuit
And the shift register specified
Data is output from the previous and next shift registers
Output buffer, and the output buffer
Performs a logical OR operation on the data
And an OR circuit that outputs the calculated data.
Address generated by the address generator in the shift register
The shift register corresponding to inputs the output of the OR circuit
A graphic drawing device figure characterized by being stored sequentially from the end
It is.

[0012]

According to the first aspect, the address of the first memory is changed.
Data is read from the corresponding address when
Is done. Further, the address adjacent to the address is the second
Of the first memory
Out of the data read out from the
Designated by the second address generation circuit of the second memory
Is written to the address. Therefore, the second memory
Adjacent to the first specified address in the first memory
To the address specified first in the first memory.
Data of a predetermined value is written in the
The figure stored in the memory is enlarged.

In the second invention, the first shift register
When an address is specified, the shift register and its
Data from the shift register adjacent to the shift register
Is output. An OR circuit is applied to this data.
By performing a constant OR operation, the second shift register
Data after operation is stored in the register at the first specified address.
Are sequentially stored. Therefore, a plurality of first shift registers
After performing this process for all of the
The second shift register includes a plurality of first shift registers.
The figure represented by the data stored in the shift register
Stores data representing a figure enlarged in the direction in which it is arranged
It will be.

In the third invention, the address of the shift register is
When the shift register is specified, the shift register and the shift
Data is output from the output end of the shift register adjacent to the register.
Is output. This data is processed by
Performs a predetermined OR operation to input the shift register.
Data after the operation is sequentially stored from the power end. Accordingly
This process is performed for all of the shift registers.
After the shift register becomes
The figure represented by the data stored in the shift register
Stores data representing a figure enlarged in the direction in which it is arranged
It will be.

[0015]

FIG. 1 is a block diagram showing an embodiment of a graphic drawing apparatus according to the present invention. The graphic drawing apparatus shown in FIG. 1 includes a first dot matrix 1 for storing a graphic to be thickened, a second dot matrix 2 for storing a thickened graphic, and a timing counter 3 for generating a timing signal. A horizontal address counter 4 for generating a horizontal address signal of the first dot matrix 1, a vertical address counter 5 for generating a vertical address of the first dot matrix 1, and a horizontal address counter of the second dot matrix 2. A horizontal / vertical address generator 6 for generating a vertical / vertical address signal and a display device 7 are provided.

The first dot matrix 1 has xe + 1 (0 to xe) in the horizontal direction and ye + 1 (0 to xe) in the vertical direction.
Ｙye) are provided.
The first dot matrix 1 outputs data "1" or "0" from a designated address according to address signals (1) and (2) generated by the horizontal and vertical address counters 4 and 5. Note that “1” indicates a case where dots are plotted, and “0” indicates a case where dots are not plotted.

As in the first dot matrix 1, the second dot matrix 2 has xe + 1 (0) dots in the horizontal direction.
To xe), and a storage area in which ye + 1 (0 to ye) dots can be plotted in the vertical direction. The second dot matrix 2 writes "1" at an address specified by the address signals (4) and (5) generated by the horizontal / vertical address generator 6. Also, it outputs data "1" or "0" written to the designated address.

The timing counter 3 generates timing signals S1 to S5 as shown in FIG. In FIG. 2, t1 to t5 indicate output timings of the timing signals S1 to S5.
Circulate at t5 hours.

The horizontal address counter 4 generates three horizontal address signals x-1, x, x + 1 in response to a timing signal S5 from the timing counter 3.
The address signal x corresponds to the address signal (1) described above. Further, x-1 and x + 1 are addresses before and after x. The horizontal address counter 4 is reset when the value of x exceeds xe, and outputs a signal (6) to the vertical address counter 5 to update the content (y + 1 ← y).

The vertical address counter 5 generates vertical address signals y-1, y, y + 1 in response to the signal (6) from the horizontal address counter 4. The address signal y corresponds to the address signal (2) described above. y-1 and y + 1 are addresses before and after y. The vertical address counter 5 is reset when the value of y exceeds ye.

The horizontal / vertical address generator 6 includes two-input AND gates A1 to A10 and a multi-input OR gate O1.
And O2. The AND gate A3 performs a logical product of the address signal x and the timing signal S1. The AND gate A4 calculates the logical product of the address signal x-1 and the timing signal S2. The AND gate A5 calculates the logical product of the address signal x and the timing signal S3. AND gate A6
Takes the logical product of the address signal x + 1 and the timing signal S4. The AND gate A7 performs a logical product of the address signal y-1 and the timing signal S1. The AND gate A8 takes the logical product of the address signal y and the timing signal S2. The AND gate A9 calculates the logical product of the address signal y + 1 and the timing signal S3. The AND gate A10 performs a logical product of the address signal y and the timing signal S4.
The OR gate O1 calculates the logical sum of the outputs of the AND gates A3 to A6. OR gate O2 is AND gates A7 to A10
OR the outputs of The AND gate A1 takes the logical product of the output of the first dot matrix 1 and the output of the OR gate O1, and generates an address signal (4) when the output of the first dot matrix 1 is "1". AND
The gate A2 performs an OR operation with the output of the first dot matrix 1
The logical product with the output of the gate O2 is obtained, and when the output of the first dot matrix 1 is "1", a vertical address signal (5) is generated.

Next, the operation of the figure drawing apparatus of FIG. 1 will be described. It is assumed that a target graphic has already been drawn in the first dot matrix 1, and all dots are clear, that is, all dots are "0" in the second dot matrix. Further, the timing signal S1
S5 are output several times, and m is stored in the horizontal address counter 4 and n is stored in the vertical address counter 5. Therefore, the dot at the address (m, n) of the first dot matrix 1 is selected, and when that dot is "1 (= on)", the output signal (3) of the first dot matrix is "1". Become. Also, the dot is “0”
(= Off) ", the output signal (3) becomes" 0 ".
The horizontal address signals m-1, m, m + 1 and the vertical address signals n-1, n, n + 1 are ANDed.
It is provided to one input terminal of gates A3 to A10. t
At time point 1, only AND gates A3 and A7 open their gates in response to timing signal S1. At time t2, only AND gates A4 and A8 open their gates in response to timing signal S2. At time t3, only AND gates A5 and A9 open their gates in response to timing signal S3. At time t4, the timing signal S4
Only AND gates A6 and A10 open the gates. Therefore, the horizontal address signal applied to the AND gate A1 is m at t1, m-1 at t2, m at t3, and m + 1 at t4.
Similarly, the address signal applied to AND gate A2 is t
1, n-1 at t2, n + at t3
It becomes n at 1, t4. At this time, if the output signal (3) of the first dot matrix 1 is “1”, AND
Since the gates A1 and A2 are open, the address signals (4) of the second dot matrix 2 are set in accordance with t1 to t4.
(5) is (m, n-1), (m-1, n), (m, n +
1), (m + 1, n), and the dots of the second dot matrix 2 located at positions corresponding to the upper, lower, left and right dots of the dots that are "on" in the first dot matrix 1 are turned "on". .

If the output signal (3) of the first dot matrix 1 is "0", the AND gates A1 and A2 are closed and no address is output. Therefore, the contents of the second dot matrix 2 do not change. The timing counter 3 outputs the signals S1 to S as shown in FIG.
5 are sequentially output. When the signal S5 is output, the first dot matrix 1 and the second dot matrix 2 are output.
The update instruction is given to the address counter 4 for controlling the horizontal direction, and the process proceeds to the next dot. When an update instruction is given when the value of the horizontal address counter 4 is xe, the horizontal address counter 4 is reset and a signal (6) for giving an update instruction to the vertical address counter 5 is output. In this way, the dot selected in the first dot matrix 1 moves to the next row. Then, the counter value of the vertical address counter 5 is y
In the case of e, the process ends when an update instruction is given by the signal (6).

Next, the data stored in the second dot matrix 2 is given to the first dot matrix 1,
Clear all the dots in the dot matrix. The line width can be further increased by repeating the above-described shift operation. By repeating this cycle several times, a figure having a desired line width can be obtained.

In the above-described embodiment, the figure to be subjected to the second bold line conversion is the first dot matrix from the second dot matrix.
Are transferred to the first dot matrix, but instead of transferring the data of the second dot matrix to the first dot matrix, the figure drawn on the second dot matrix is set as a figure to be bolded, An even-numbered bold figure may be drawn on the first dot matrix.

FIG. 3 is a block diagram showing an embodiment of the graphic drawing apparatus according to the second invention. The figure drawing apparatus shown in FIG. 3 includes a first dot matrix 1 'for storing a figure to be thickened, a second dot matrix 2' for storing a thickened figure, an output buffer 21, and an address counter. 22, a delay register 23a to 23d, an OR gate 24, a clock signal generator 25, and a display device 7.

The clock signal generator 25 has three clock signals CLK1, CLK2 and CLK3 as shown in FIG.
Occurs. The clock signal CLK1 is applied to a first dot matrix 1 ', the clock signal CLK2 is applied to a second dot matrix 2', and the clock signal CLK3 is applied to each of the delay registers 23a to 23d. In FIG. 4, t _{0 to} t _xe correspond to 1-bit output time of the first and second dot matrices 1 ′ and 2 ′. t _S is a period for first resetting the delay registers 23a to 23d in each cycle.

The first dot matrix 1 'is xe + 1 (0 to 0) in the horizontal direction, similarly to the dot matrix of FIG.
xe), and has an area for plotting ye + 1 (0-ye) dots in the vertical direction. The first dot matrix 1 'includes a shift register R ₀ to R _ye of each bit length (xe + 1). Each of the shift registers R _{0 to} R _ye sequentially outputs graphic data of each bit in response to the clock signal CLK1. Although not shown, the outputs of the shift registers R _{0 to} R _ye are input to the shift registers.

Each of the second dot matrices 2 'has a bit length (xe) similarly to the first dot matrix 1'.
It includes a shift register Q ₀ ~Q _ye +1). Each of the shift registers Q _{0 to} Q _ye sequentially stores data supplied from the OR gate 24 in accordance with the clock signal CLK2.

The address counter 22 has first and second
For sequentially specifying the shift registers R _{0 to} R _ye and Q _{0 to} Q _ye of the dot matrices 1 ′ and 2 ′ are supplied to the first and second dot matrices and the output buffer 21.

The output buffer 21 includes shift registers R ₀ to R ₀ .
Register designated by the address counter 22 of the R _ye R _y and before and after the shift register R _y-1, R
The output of _{y + 1} is output as output signals (7), (8), and (9). This signal is outputted only in a time zone of t ₀ ~t _xe shown in FIG. Although not shown for the sake of simplicity, the output signal (7) is set to 0 when the address specified by the address counter 22 is 0, and the output signal (9) is set when the address is ye. Is set to 0.

The delay registers 23a to 23d are 1-bit long registers. The delay register 23a delays the output signal (7) by one bit, and
With c, the output signal (8) is delayed by 2 bits, and the delay register 23d delays the output signal (9) by 1 bit.

The OR gate 24 includes a delay register 23a,
The output of 23c and 23d and the output signal (8) are ORed. The output of the OR gate 24 is the address counter 2
It is given to the designated shift register Q _y by 2.

Next, the operation of the graphic drawing apparatus shown in FIGS. 3 and 4 will be described. The target graphic has already been drawn in the shift registers R _{0 to} R _ye of the first dot matrix 1 ′, and all the shift registers Q _{0 to} Q _ye of the second dot matrix 2 ′ are clear, that is, all Is set to "0". Assuming that the address counter 22 indicates a certain address "y" to the first and second dot matrices 1 'and 2', the output buffer 21 outputs the shift register R _y-1 as the output signal (7). , An output signal (8) and a shift register _Ry as an output signal (9).
Outputs _{y + 1} . The output signals (7) and (9) are output to the OR gate 24 with a delay of one clock since they pass through the delay registers 23a and 23d, respectively. But,
The output signal (8) is output to the OR gate 24 as it is and a signal delayed by two clocks is also output. In this way, the OR gate 24 calculates _{Ry-1, n} or _{Ry, n-1} or _{Ry, n + 1} or _{Ry + 1, n,} where n is an arbitrary x coordinate on the dot matrix. Point. And output to the shift register Q _{y, n} . When the clock signal CLK1 is output the address y output by the address counter 22, figure and thicker the portion that has been stored in the shift register R _y of the original shape is obtained in the shift register Q _y. By repeating this operation from 0 to ye for the address y, the bold-lined figure is stored in the second dot matrix 2 '.

According to the above-described graphic drawing apparatus, since the graphic drawing apparatus shown in FIG. 1 can perform drawing on a line-by-line basis as compared with the case where the graphic drawing apparatus of FIG. it can.

FIG. 5 is a block diagram showing an embodiment of the third invention. This graphic drawing apparatus differs from the graphic drawing apparatus of FIG. 3 in that the second dot matrix 2 'is omitted and that an address for writing data from the address counter 22 to the dot matrix 1' is given. It is that you are. Other circuits are the same as those in FIG. 3, and are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

In operation, the OR gate 24 performs an OR operation on the position data obtained by shifting the dot position data of the original figure by one dot vertically, horizontally, and one dot at a time, and provides the result to the dot matrix 1 '. When the original dot position data is output from the shift register R _y , the address counter 22 sets the shift register R as a write shift register.
Select _y-1 . The writing to the shift register _Ry-1 is performed for the following reason.

As described above, to obtain a result of a certain line,
You need the original data for that row and the rows before and after it.
That is, to obtain the result of the y-th row, the data of the y-th row is also required. Therefore, the obtained result is stored in the shift register R
_This is because it cannot be stored in _y, but if it is the shift register R _y-1 one row before, it does not affect other rows.

Therefore, when the address counter 22 specifies the address y, the OR gate 24 outputs _Ry-1 or _Ry right or _Ry left or _{Ry + 1} . This data is stored in the shift register _Ry-1 . Here, R _y right and R _y left are obtained by shifting the contents of each shift register right and left.

In the next cycle, the address counter 22
When +1 is designated, the OR gate 24 outputs _Ry or _{Ry + 1} right or _{Ry + 1} left or _{Ry + 2} . This is stored in the shift register _Ry .

However, in the case where the target figure is made thicker by one dot around the target figure, it is necessary to shift the target figure by one dot below a predetermined position.

According to the embodiment of FIG. 5, the second dot matrix shown in FIG. 3 is not required, so that the use efficiency of the memory can be improved and the cost can be reduced.

FIG. 6 shows the relationship between the arrangement of the original figure and the arrangement of the generated figure in the first dot matrix. When adding an n-fold thickness to the original figure, n
You must have an area that is large by the dot. A figure having a desired thickness can be obtained by drawing the original figure in the center of the area and making the periphery thicker one by one by the method shown in FIGS.

[0044]

According to the first aspect of the present invention, the second memory
Adjacent to the first specified address in the first memory
Address is the address specified first in the first memory.
Data of a predetermined value is written out of the
The figure stored in the memory is enlarged. For example
By repeating this, the line width can be increased by the desired amount.
Can be. This process is performed in a hardware
High-speed because it can be performed based on the
I can do it.

In the second invention, the first shift register
Second shift register after processing for all
Within the data stored in the first shift register
The figure to be displayed is enlarged in the direction in which the shift registers are arranged.
Data representing the drawn figure can be obtained. Accordingly
For example, the line width of a character
Can be fattened in the direction. This process is hardware
Row (or column) based on a predetermined timing signal
It is fast because it can be done in units.

In the third invention, all of the shift registers
After processing, the shift register
The figure represented by the stored data is
It is possible to obtain data representing a figure enlarged in the arrayed direction.
Can be. Therefore, for example, the line width of characters
The thickness can be increased in the direction in which the shift registers are arranged. This
In this case, it is not necessary and necessary to prepare two sets of shift registers.
The required storage capacity can be reduced. Also, this processing is
A, based on a predetermined timing signal,
It is fast because it can be done in column) units.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a graphic drawing apparatus according to the first invention.

FIG. 2 is a waveform diagram of a timing signal output from the timing counter of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of the second invention.

FIG. 4 is a waveform diagram of a clock signal applied to each circuit of FIG. 3;

FIG. 5 is a block diagram showing an embodiment of a graphic drawing apparatus according to the third invention.

FIG. 6 is a diagram illustrating a relationship between an original figure and a region to be thickened in a first dot matrix.

FIG. 7 is a diagram for explaining the concept of thickening.

FIG. 8 is a diagram for explaining a conventional thickening method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first dot matrix 2 second dot matrix 3 timing counter 4 horizontal address counter 5 vertical address counter 6 horizontal / vertical address generator 7 display device 21 output buffer 22 address counter 23 a to 23 d delay register A 1 to A 10 AND gate O 1 O2, 24 OR gate

Continuation of front page (58) Fields investigated (Int.Cl. ⁶ , DB name) G06T 5/00 G09G 5/24 630 H04N 1/387 B41J 2/485-2/515

Claims (3)

(57) [Claims] A first timing signal; a first timing signal;
Second timing at a frequency equal to or higher than the frequency of the imming signal
And a first counter and a second counter, each of which can store a dot matrix.
And Mori, in response to the first timing signal, the first memory
A first address generating circuit for sequentially designating each address, and receiving an address from the first address generating circuit,
The second memory is responsive to a second timing signal.
Of addresses adjacent to the above address in a predetermined order.
And a second address generating circuit for selectively outputting the second timing signal, wherein the second memory responds to the second timing signal.
And read from the address of the first memory
Only the data having a predetermined value is stored in the second address.
Write to the address generated by the source generation circuit, and further, among the data stored in the second memory,
Means for providing a predetermined value to the first memory
A graphic drawing device characterized by the above-mentioned . 2. A plurality of first shift registers, a plurality of second shift registers, and an address for sequentially designating each of the first shift registers.
A generation circuit, and the address generation circuit of the first shift register.
Shift register specified by the address where the path occurs
And the shift registers before and after the shift register
An output buffer for sequentially reading data, and a predetermined logic for data output from the output buffer.
Logic that performs sum operation and outputs data after logical operation
And a sum circuit for generating the address of the plurality of second shift registers.
The shift register corresponding to the address generated by the circuit is
The output of the OR circuit is sequentially stored.
Graphic drawing device . 3. A plurality of each having an input end and an output end.
Shift registers and address generation times for sequentially specifying each of the shift registers.
The address generator circuit of the shift register.
The shift register specified by the generated address
Data from the shift register before and after the shift register
And an output buffer for sequentially reading data from the output terminals, and a predetermined logic for data output from the output buffer.
Logic that performs sum operation and outputs data after logical operation
A plurality of shift registers;
The shift register corresponding to the generated address is
The output of the logical sum circuit is stored sequentially from the input terminal.
A graphic drawing device to be used.