RU1772806C - Image processor - Google Patents

Abstract

The invention relates to techniques for digital signal processing, in particular to image processing devices, and can be used in information display devices. The purpose of the invention is to increase speed. An input register, an adder, a synchronizer, a symbol information generating unit, a graphic information generating unit are introduced into a device comprising a random access memory unit, a microprogram control unit, a microprogram memory unit, a clock generator, an arithmetic device. The essence of the proposed device is that due to the implementation of parallel processing and display of information and there is no need to synthesize the sign, the productivity of the device has increased compared to the prototype. 1 ill. sl c

Description

The invention relates to digital signal processing, in particular to image processing devices, as well as information display devices.

A device is known comprising a control unit, address register, familiarity counter, familiarity line counter, character string counter, synchronization unit, shift register, character generator, buffer registers, address switch, clock, RAM unit 1.

The disadvantage of this device is the appearance of noise on the indicator screen during editing and data exchange caused by asynchronous interruption of the regeneration process.

A device is known comprising a decoder, a memory, an address counter, a character generator, a point counter, a character counter, a television line counter, a start address generator and a second memory, switch 2.

In the device, the working field of the screen is divided into a large number of dots or image elements. Each screen element corresponds to one bit in RAM. To increase the speed, an address switch, a start address shaper, and a second memory are introduced into it. At the same time, the address counter provides direct addressing of the random-access memory device when downloading and reading data. The switch provides switching of the download address and sign code at the moments of loading and reading the second memory, which is intended for storage and regeneration and information displayed on the screen of a CRT.

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The disadvantage of this device is its low speed and the inability to recalculate coordinates.

Closest to the proposed one is a device comprising a micro-software control unit, a memory unit, a clock generator, an operation unit, a constant memory unit, a state register, a RAM unit 3.

This device processes the information received at the input of the device, namely, recalculating coordinates, accumulating information, arithmetic and logical operations on the displayed data, and converting the displayed information.

The disadvantage is the low speed, because All of the above functions are performed sequentially in time on the same hardware, therefore, after the arrival of the next input coordinates, a large number of clock cycles of the device is necessary to obtain the output value.

The purpose of the invention is to increase the speed of action,

The goal is achieved by the fact that in the image processing device comprising a random access memory unit, a microprogram control unit, a microprogram memory unit, an arithmetic device, a clock generator, the output of which is connected to the first inputs of the arithmetic device and the microprogram control unit, the first output of which is connected with the address input of the microprogram memory unit, the output of which is connected to the second input of the microprogram control unit, the third input of which is connected to the first Odom / / output of the arithmetic unit; input register, adder, synchronizer, character information generation unit and graphic information generation unit are introduced, the second input / output of the arithmetic device, RAM input / output, information inputs of the character information generation and graphic information generation units are combined and connected to the output of the input register, the information input of which is connected to the input of the device, and the sync input is connected to the second output of the microprogram control unit, the third, fourth, fifth, neck the seventh and seventh outputs of which are connected respectively to the device output i of the device, to the recording input of the random access memory unit, the first and second control inputs of the sign information generation unit and to the gate input of the graphic information generation unit, whose clock input and information output are connected respectively to the output clock generator and with the first input of the adder, the second input of which is connected to the information output of the sign information generation unit, whose address input is it is single with the address output of the graphic information generation unit and with the first input of the synchronizer, the second input and output of which are connected respectively to the output of the adder and the output of the device, and the sign information generation unit contains an address and data switch, a memory of the sign device, a character generator, the output of which is information output of the block, the address input of the block is connected to the address input of the address and data switch, the information input of which is the information input of the block, and once The input address of the address and data switch is the first control input of the unit, the output of the address and data switch is connected to the address and information inputs of the memory sign device, the access input of which is the second control input of the unit, and the output is connected to the first input of the character generator , the second input of which is connected to the address input of the block, and the output is connected to the output of the block, in addition, the block for generating graphic information contains a data register, an address m data switch, a memory graphic device in, an address counter, the counting input of which is the clock input of the block, the output of the address counter is the address output of the block and connected to the address inputs of the memory graphic device and the address and data switch, the output of which is connected to the input of the memory graphic device, the output of which is the information output of the block, the information input of the address and data switch is connected to the output of the data register, the information input of which is the information input of the block, and the gate input is robotic input block.

The drawing is a block diagram of an image processing apparatus.

The image processing device comprises an input register 1, an arithmetic device 2, a firmware control unit 3, a firmware memory unit

4, random access memory unit 5, clock generator 6. character information generating unit 7, adder 8, synchronizer 9, graphic information generating unit 10, wherein the character information generating unit 7 includes an address and data switch 11, a symbol storage device 12, a character generator 13. And the graphic information generating unit 10 contains a data register 14, an address and data switch 15, a graphic memory device 16, an address counter 17,

The device operates as follows.

The operation of the entire device is controlled by the microprogram control fleas 3 according to the microprograms located in the microprogram memory 4. When the device is turned on, the microprogram apparatus makes the initial installation of all nodes and switches to a waiting cycle for an array of input coordinates. In this case, a READY signal is generated, which means that the device is ready to receive coordinates.

The input coordinate array is preceded by a service word that contains the sign of the beginning and size of the processed coordinate array, the scale and image processing mode. The service word is stored until the next array of coordinates is received and is used in processing.

The entire array of input coordinates is written to RAM 5. Then, the device switches to coordinate processing. The output from the arithmetic device is entered into the graphic information generation unit, and the explanatory sign information (scale, time or frequency domain, size of the processed coordinate block, etc.) is entered into the symbol information generation unit, Coordinate codes X n Y stored in the graphic information generator at the same time as outputting information from the output of the arithmetic device. The outputs of the blocks of the shapers of the symbolic and graphic information go to the inputs of the adder 8, the total signal from the output goes to the input of the synchronizer 9, It provides the conversion of coordinate codes into a serial code and synchronously generates sequences of coordinate codes together with line and frame pulses. The output signal can directly fed to a raster scan imaging device.

The character information generating unit 7 operates as follows.

Codes of sign (information) information and its address to the unit are received from the output of the arithmetic device by a control signal from the output of the microprogram control unit, by the signal from which information is also loaded into the sign memory device 12.

In the case when there is no loading of the sign information codes, the read address from the output of the address and data switch 11 is supplied to the sign memory 12, the read codes go to the input of the character generator 13. The output codes of which go to one of the inputs of the adder 8. The unit for generating graphic information 10 works as follows. Codes of coordinates X and Y from the output of arithmetic device 2 are recorded in the data register 14 and at the same time, with a delay of a clock cycle, this information is stored in the graphic memory device 16. The address and data switch 15 switches the addressing of the graphic memory device 16 alternately into recording mode or regeneration (reading). The regeneration (reading) address is formed by the address counter 17, the counting input of which receives the clock from the output of the clock 6. The output information (during regeneration) is supplied to the adder 8.

Claims (1)

The proposed device can improve performance by implementing parallel processing and display of information, there is no need to synthesize the sign and simultaneously generate the X and Y coordinates in the display mode of graphic information. Formula of the Invention A device for processing images containing a random access memory block, a firmware control block, a block microprogram memory, arithmetic device, clock generator, the output of which is connected to the first inputs arithmetically about the device and the firmware control unit, the first output of which is connected to the address input of the firmware memory unit, the output of which is connected to the second input of the firmware control unit, the third input of which is connected to the device start input, the input-output of the firmware control unit is connected to the first input-output arithmetic device, characterized in that, in order to improve performance, an input register, adder, synchronizer, sign information generating unit are introduced into it and a unit for generating graphic information, the second input-output of an arithmetic device, the input-output of a random access memory unit, the information inputs of the sign information generation and graphic information generation units are combined and connected to the output of the input register, the information input of which is connected to the input of the device, and the clock input - with a second output of the microprogram control unit, the third, fourth, fifth, sixth and seventh outputs of which are connected respectively to the readiness output of the device, to input to write a random access memory block, the first and second control inputs of the sign information generation unit and to the building input of the graphic information generation unit, the clock input and information output of which are connected respectively to the output of the clock generator and the first input of the adder, the second input of which connected to the information output of Olok forming the sign information, the address input of which is connected to the address output of the block for generating graphic information and with the first input ronizatora, a second input and whose output is connected respectively to the output of the adder and the output device, the character information generating unit comprises a switch address and data, a memory device landmark, znakoge- (erator whose output is information output of the block, the address input of the block is connected to the address input of the address and data switch, the information input of which is information input of the block, and the enable input of the address and data switch is the first control input of the block, the output of the address and data switch is connected to the address and information inputs of the storage sign device, the access input of which is the second control input of the unit, and the output is connected to the first input of the character generator, the second input of which is connected to block input address, and the output with the block output, in addition, the graphic information generating unit contains a data register, an address and data switch, a graphic memory device, a counter address, the counting input of which is the clock input of the block, the output of the address counter is the address output of the block and connected to the address inputs of the memory graphic device and the address and data switch, the output of which is connected to the input of the memory graphic device, the output of which is the information output of the block, the information input of the address and data switch is connected to the output of the data register, the information input of which is the information input of the block, and the gate input is the gate input block house. iO 1