SU1339625A1 - Graphic information output device - Google Patents

Abstract

The invention relates to computing and may be used by the user to display information. The purpose of the invention is achieved by introducing the first counter 2, the control unit 4, the second counter 8, the first register 9, the second register 10, the adder 11, the third counter 12, the multiplication unit 13, the shift register, the decoder, five triggers, two And elements, two groups elements And, the pulse generator, the fourth counter. A row counter, a decoder block, four flip-flops and an adder are also entered into the device, which allows the image displayed on the screen to be shifted in the horizontal direction. 2 hp f-ly, 6 ill. HHifJOp- mafi HatfQffbHbiu address (L JL OffOHvafft / e: writing to fig. G

Description

The invention relates to computing technology, is intended for displaying graphical information from a computer, and can be used in automation systems for designing and designing, in automated data processing, in dialog systems.

The aim of the invention is to increase the speed of the device.

Fig, 1 shows the block diagram of the device; Fig, 2 - the image of a movable floor of the screen; in fig. 3 is a diagram of the formation of free ad-15 pecaj in FIG. 4; a cylindrical interpretation of the contents of the memory block in FIG. 5; a structure of the control unit; Fig, 6 - structure of the synchronization unit, .20

The device contains a memory block 1, the first counter 2, the modulation block 3, the control block 4, the synchronization block 5, the address switch 6, the television indicator 7, the second counter 25 8, the first 9 and second 10 registers, the adder II, the third counter 12, multiplication unit 13 and one-shot 14,

The control unit 4 contains the shift register 15, the decoder 16, the first trigger 17, the first 18 and second 19 elements And, the first 20 and second 21 groups of elements And, the second 22, the third 23, the fourth 24 and the fifth 25 triggers, the third the element AND 26 and the element OR 27,

The synchronization unit 5 contains a generator of 28 pulses, a counter of 29 points, a counter of 30 lines, a block of 31 deflectors, a sixth 32, a seventh 33, a 40 eighth 34 and a ninth 35 trigger and an analog adder 36,

The device works as follows

The synchronization unit 5 generates 45 pulses corresponding to the required screen rasterization of the television indicator, and controls the scanning of the latter. These pulses go to control unit 4, drying, and there is a temporary reference to the television clock signal,

Original image stored

in computer memory, has dimension 2

tons of points horizontally and z points along its

0 °. oP

verticals, with 2 z + / (fig. 2),

The size of the image displayed on the screen is 2 pixels.

35

five

five

about

0

50

e

five

horizontals and 2 points vertically, where is the word size of the memory block; 2 - the number of words placed on the visible course of the scanning line; 2 - number of image lines,

The capacity of memory block 1 (2 +1) x2 words. In memory block G each point of the image corresponds to one bit encoding the brightness of the point.

The device provides a horizontal view of the original image by the screen window — in increments of one block of the memory block, which is carried out as follows; the computer performs a scan of the original picture file, injects parts of the elements that fall into the screen window starting from input start address in the first register. Then, the computer forms a raster representation of a part of the image that has fallen into a 2 x 2 window and writes it into a memory block. At the same time, the recording control signals of the words 4 are fed to the recording control input of the block, the addresses of the words being written are fed to the first switch inputs of the switch, and the information to be written to the information input of the memory block

Information is read from the memory block as follows.

On the visible course of the frame, the lower-order sync pulses come from the synchronization unit 5 to the clock input of the first counter 2. These pulses are used to record the data contained in. the first register of the address A .. in the first counter 2, which has a conversion factor of 2 +, however, only 2 combinations are counted in the visible line of the line, starting with. (FIG. 2). These combinations are determined by the pulses +1 coming from the synchronization unit 5 (FIG. 3, pos. 4), with a period equal to the cycle time of the memory block. The first counter 2 is triggered by the falling edge of the clock pulses arriving at its input.

The last combination of the first counter is formed immediately after the end of the apparent stroke of the line (FIG. 3, pos. 2). In this case, the one-shot produces a pulse (FIG. 3, pos. 3), which records address A, 5 stored in the first counter. 2, in the second register 10,

The second counter 8 recalculates the lines of the image displayed on the screen on the visible frame, has a conversion factor of 2 and is set to 0 by a frame extinguishing pulse signal. The outputs of the first 2 and second 8 counters are connected through the first and second inputs of the address switch to the address inputs of memory block 1 These and serve as word reading addresses. The control signals necessary for reading form the control unit under the action of synchronizing pulses coming from the synchronization unit.

The control unit 4 operates as follows. In the read mode of information from the memory unit 1, it forms a timing diagram of the read cycle and controls the operation of the modulation unit. The time patterns of the read cycle are generated at the outputs of the shift register, which during the read cycle advances logical 1, and at the end of the cycle is reset to zero by a signal from the output of the decoder that produces a time sequence of pulses during the read cycle. The same trigger signal transfers the first trigger, which determines which register and multiplexer of the modulation block receives recording signals from the outputs of the first and second And elements and control signals from the multiplexers from the outputs of the first and second groups of And elements,

When the write control signal is received, the fourth trigger 24 is set to 1, which is fed to the control input of the fifth trigger 25. The latter, under control of the signals from the decoder, selects a write pulse that connects the address switch in such a way that its output is write addresses. In addition, the recording pulse, the passage through the OR element 27 and the third element AND 26 are fed to the recording input of the memory unit 1, where the information is recorded.

: In the recording mode, the record control signal sets the second trigger 22 to state 1, which goes to the control input of the third trigger 23. According to signals from the decoder, the third trigger 23 selects a write pulse that connects its second addresses to the switch output inputs (t, e. signals from the outputs of the adder 4). In addition, the write pulse, the passage through the first OR element and the AND element, records information in memory block I, and also serves as an impulse to add 1 to the third counter 12.

The words read from block 1 of the memory are fed to the inputs of the modulation unit, where the sync pulses coming from the synchronization unit 5 to the inputs of the television indicator are converted into a serial video signal j.

The way to organize reading from memory block 1, when in line

2 + words are read, and only 2 words are displayed, allowing the contents of memory block 1 to be interpreted as a cylinder (Fig 4) with one free column wide

one word. This free word is adjacent to the first displayed word (with address A.) on the left and. with the last word displayed in the line (with the address A of the line) on the right,

Thus, to move the screen window one word to the right, it is enough to increase by one the value to bring it into the first register 9 and form a raster representation.

free column, corresponding to the segment of the original picture adjacent to the screen window with a width of 2 points and a height of 2 points. If necessary, move the screen window

to the left you need to reduce by one the value and put it in the first register 9, and in the free column add the raster representation of the area corresponding to the left

adjacent to the window segment of the original picture. The recording of this adjacent section in the memory unit 1 is carried out as follows. Pulses (Fig, 3, POS, 3) from the single vibrator come

to the input of the record of the second register 10, to the information inputs of which are connected the outputs of the first counter 2, which receive the word addresses for the memory block 1. Pulses (Fig. 3,

poses, 3) write the address of the AC-WB free word of the first line to the second register 10i Word addresses of the memory block 1 in the free column when writing is calculated by the formula

A. IA „+ 1),

 where 2;

i is the line number counted from the top edge.

When writing a raster array to a free segment of a computer, it gives signals to the recording control, and to the information inputs of memory block 1 it sequentially generates 2 words containing the raster representation of the corresponding section. The write addresses of the free column are formed in the proposed device by multiplying the contents of the third counter 12 by 2 +1 in multiplication unit 13, the output code of which is summed in the adder with the code A contained in the second register. Outputs of the adder, which forms the current address of the record. , are connected to the second inputs of the address switch and serve as the word addresses of the recorded free column of memory block 1. At the end of the recording of 2 words from the output of the third counter, the computer receives a signal of the end of the recording. The third counter triggers on the falling edge of the pulse.

Claims (2)

Invention Formula 1, A device for outputting graphical information containing a memory unit whose address input is connected to an output of an address switch, and an output connected to an information input of a modulation unit whose output is connected to an information input of a television indicator whose synchronization input is connected to a first output of a synchronization unit characterized in that, in order to improve the speed of the device, it comprises a control unit, first and second counters, first and second registers, an adder, a third counter, a multiplication unit and d-novibrator, the second output of the synchronization unit is connected to the clock input of the control unit, the third and fourth outputs of the synchronization unit are connected to the clock input and the shift input of the second counter. with the sixth output of the synchronization unit, output one-shot is connected to a clock input of the second register, the information input of which is connected to the first output of the first counter, the second output of which is connected to the information input of the second counter, the first information output of the address switch is connected to the first output of the first counter, the second information input of the address switch is connected to the output of the second counter , the third information input of the address switch is connected to the output of the adder, the first information input of which is connected to the output of the multiplication unit, and Ora data input connected to the output of the second register, multiplying block input coupled to a first output 0 of the third counter, the second output of which is the output of the recording end of the device, the information input of the third counter is connected to the first output of the control unit, the second and 5 the third outputs of which are connected to the first and second control inputs of the unit, modulation, the fourth output of the control unit is connected to the write input of the memory unit, the fifth output of the control unit is connected to the control input of the address switch, the fourth information input is the address input the device, the recording control input of the lanyard unit is the recording input of the device, the information input of the first counter is connected to the code of the first register, the input of which is the input of the initial address of the device, The Q information input of the memory block is the information input of the device, 2. The device according to claim 1, about tl and - the fact that the control unit contains a shift register ,, decoder, first trigger, first and second elements And, first and second groups of elements And, second, third, fourth and p third triggers 0 element AND, element OR, and The first output of the decoder is connected to the first inputs of the first and second elements And, the second input of the decoder is connected to the reset input of the shift register and to the single installation input of the first trigger, the direct output of which is connected to the second input of the second element And and to the first inputs of the elements And the second five the group, the inverse output of the first trigger is connected to the second input of the first element And, and to the first inputs of the elements AND of the first group, the third output of the decoder is connected to the single installation inputs of the third and fifth triggers, the direct outputs of which are connected to the inputs of the OR element and are fifth the output of the block, the output of the OR element is connected to the first input of the third element, AND, the second input of which is connected to the first outputs of the shift register, the zero setting input of the third trigger is connected to the direct output of the second trigger a, the zero setting input of which is connected to the inverse output of the third trigger, the zero setting input of the fifth trigger is connected to the direct output of the fourth trigger, the zero setting input of which is connected to the inverse output of the fifth trigger, a single setting input of the fourth trigger and a single setting input of the second trigger are the control inputs of the block record, the first input of the decoder, the second inputs of the elements of the first and second groups, the second input of the decoder and the clock input of the shift register are The clock input of the block, the direct output of the third flip-flop is the first output of the block, the outputs of the first and second elements of AND are the second output of the block, the output of the elements of the first and second five 0 five 0 five the groups are the third output of the block, the second output of the shift register and the output of the third element And are the fourth output of the block, 3, the apparatus of claim 1, wherein the synchronization unit comprises a pulse generator, a fourth counter, a row counter, a decoder unit, sixth, seventh, eighth and ninth triggers and an adder, the output of which is the first output of the unit, the outputs of the sixth and the ninth flip-flops are connected to the first and second inputs of the adder and are the third and fourth blocks of the block, the outputs of the seventh and eighth flip-flops are connected to the third and fourth inputs of the adder, the output of the eighth trigger is the sixth block output, the inputs of the sixth, nine second, seventh and eighth triggers are connected respectively to the first, second, third and fourth outputs of the decoder unit, the first input of which is connected to the output of a row counter, the input of which is connected to the first output of the fourth counter, the second output of which is connected to the second input of the decoder unit, generator output the pulses are connected to the information input of the fourth counter, the third output of the fourth counter is the fifth output of the block, the output of the pulse generator and the second output of the fourth counter are the second m block output. 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