SU1361615A1 - Device for representing information on television display screen - Google Patents

Abstract

The invention relates to automation, control systems, computing and television equipment, and can be used in the output of graphic information on the screens of multi-purpose television video terminal devices. The purpose of the invention is to increase the accuracy of the device. For this, an analog-digital converter 1, a block of 2 And elements, a block of 3 registers, a decoder 9, elements 4, 17 and 27 of OR, an encoder 10, dividers 21, 26 and 31 frequencies, elements 12, 24, 22 and 23 are entered into the device. And, element 28 is NOT, shift registers 13 and 25, selectors 6 and 29, е S (Л С / 0 05 05 cf

Description

trigger 16 with corresponding functional connections. The invention makes it possible to simply and reliably record and display on the screen of a television indicator with a limited bandwidth contour information with high accuracy determined by the capability of the input ADC and considerably exceeding the limits of display accuracy of information

The invention relates to automation, control systems, computing and television equipment and can be used in the output of graphic information on the screens of television video terminal devices of a wide purpose.

The purpose of the invention is to increase the accuracy of the device.

The drawing shows the functional diagram of the device.

The device contains an analog-to-digital converter (ADC) 1, block 2 of elements And, block 3 of registers, the first

the element OR 4, block 5 operational PA

m tee, first selector 6, first block

7 elements OR, counter 8 clock pulses, decipher 9, encoder 10, switch 11, first AND 12 element, first shift register 13, write address and read address counters 15, trigger 16, second OR element .17, video signal generator 18, television indicator 19, clock generator 20, the first frequency divider 21, the third 22, the fourth 23 and the second 24 AND elements, the second shift register 25, the second divider 26 of the second, the third element OR 27, the HE element 28, the second selector 29, the second block 30 elements OR, the third divider 31 frequency and sync driver 32.

The first 7 and second 30 blocks of the OR elements perform the function of expanding the information bits by as many times as the shear frequency produced by the clock generator.

the torus would be entered into the regeneration RAM block without the shift codes. This is achieved by horizontally shifting each element of the image discretization floor on the CRT screen adaptive to the image, i.e. a shift is made to distances less than one horizontal sampling interval, which leads to an increase in accuracy. 1 il.

20 is greater than the horizontal sampling rate of the image.

Generator 20 also produces

frequency 2 MHz, obtained from dividing the fundamental frequency.

The device works as follows.

With the frequency produced by the generator 20, the sampling of the input binary signal acting on the information input of the ADC 1, in a digital code, go to block 2 of the elements I.

With the same frequency that operates on the clock input of the A / D converter 1, these samples are written alternately to the registers of block 3, the recording sequence in which is provided by connecting the registers of elements And block 2 to the first input, the first input of which receives signals from the decoder 9 (the decoder outputs are excited with the frequency specified by the generator 20, in the sequence of changing the state of the counter 8, the output of which is connected to the input of the decoder 9).

The presence in the block of 3 registers of units means a high level of signal,

At the output of the A / D converter 1, a unit is recorded in the corresponding cell of the RAM 5, otherwise a zero is written.

The state of the block 3 of registers, which means at what point in time (with discreteness of the clock frequency of the generator 20) the input signal has changed, is encoded by the encoder 10 and is written in the form of a binary code

3136

in the same cell of block 5, as the record from the first element OR 4, but in other bits. The value of these additional bits is the shift code of the start of the signal display when it is read from block 5 (regeneration memory) with respect to the location of these signals in the nodes of the image decomposition matrix with a fixed location of cells in the screen field.

As a result, it becomes possible to record contour information in the regeneration memory with an accuracy exceeding the discreteness of its representation of the NIN as a bitmap, which is determined by the maximum permissible bandwidth of the television indicator 19.

The clock frequency of the generator 20 is higher than the frequency of recording information in block 5 and the frequency of regeneration of its contents on the screen of indicator 19.

In order to ensure synchronization of the recording of information in block 5 with the process of its sampling ADC 1, the frequency of the generator 20 is divided to the required value by the first frequency divider 21.

In order to ensure a stable reading of the memory cells of the block 5 during the regeneration process, the frequency of the generator 20 is divided by the second frequency divider 26.

The third frequency divider 31 divides the reference frequency to the value required for the operation of the clock generator 32 (e.g., 2 MHz).

The recording in the sampling unit 5 of the input signal is carried out in the time interval of the reverse sweeps, therefore during recording the picture 19 displayed on the screen does not disappear.

The pulses of the SGI (lowering damping pulse) and OIG (frame damping pulse), arriving at the inputs of the OR element 27 from the corresponding outputs of the clock generator 32, are OR connected and through the switch 11 are connected to the address input of the block 5 the record address counter 14.

In the absence of the OIG and OIG (during the forward stroke of the sweeps), the switch 11 connects the address input of the unit 5 to the reading address counter 15,

The pulse mixture of OIG and SGI through the switch 11 is fed to the second input of the element And 22 and ensures the passage through it of the frequency

five

Q

five

0

50

five

54

recording from the output of the first divider 21 frequencies to the summing input of the counter 14 records.

At the same time, the pulses of the OIG and SGI, inverted by the element HE 28, arrive at the fourth element I 23 and prohibit the passage to the summing input of the counter 15 of the reading address of the reading frequency from the output of the second frequency divider 26.

To ensure the stability of the image on the screen of the indicator 19, the counter 15, by the time the display starts, each time is reset to the zero setting input by the OIG pulses.

The information read from block 5, through the element 12 or the element 24 and goes to the information input of one of the selectors 6 or 29.

Two channels, the first of which contains an element AND 12, a selector 6, a block 7 of elements OR, a shift register 13, and the second an element And 24, a selector 29, a block 30 elements OR, a shift register 25, are organized for varying work in time when a sequence of image sampling elements is displayed on the screen.

From even cells information is entered into one of the shift registers, from odd ones into the other.

The keys are the elements And 12 and 24, which are controlled by the signal from the direct and inverse outputs of the trigger 16. The counting input of the trigger 16 receives the same frequency as that of the summing input of the counter 15 of the reading address.

The OR element 17 combines the outputs of the shift registers 13 and 25 and delivers a signal to the video signal generator 18, which is summed with the full television synchromesh signal that comes from the clock generator 32.

In accordance with the shift code that arrives at the information inputs of the selectors 6 and 29 from block 5, information is allocated at one of their outputs.

Information from the selectors is fed to that input of blocks 7 and 30 of the OR elements, which corresponds to the required horizontal image shift.

The bit of the image element is written to those bits of the shift register, within its bit grid.

which correspond to a given shift on the CRT screen.

At the output of the shift register, the duration of the image decomposition element is kept equal to what it would have been if the decomposition elements were directly supplied to the CRT with a frequency equal to the horizontal sampling frequency.

images.

I

The proposed device allows simple and reliable recording and display on the screen of a television indicator with limited bandwidth contour information with high accuracy determined by the ability of an input analog-digital converter and significantly exceeding the limits of display accuracy of information regeneration without shift codes.

Claims (1)

Invention Formula A device for displaying graphical information on a television indicator screen, containing a block of RAM, the control input of which is connected to the output of the switch, the write and read address counters, a video signal generator, syn. the logging of which is connected to the first output of the synchronous generator, and the output - to the input of the television indicator, clock counter, clock generator , different In order to improve the accuracy of the device, it contains an analog-to-digital converter, the information input of which is the device input, a clock input connected to the clock generator output connected to the counter input of the clock counter, a block of elements AND a decoder, the input of which is connected to the output of the clock counter, and the output - with the first input of the block of elements And, the second input of which is connected to the output of the analog-digital converter, the block of registers, the input of which is connected to the output of the element block Comrade Y, three elements OR, encoder, information input of which VNII1SH Order 6295/51 Circulation 433. Subscription Random polygons pr-tie, Uzhgorod, st. Design, And five 0 five and the inputs of the first element OR are connected to the output of the register block, and the outputs of the first element OR and the encoder are respectively connected to the address and information inputs of the RAM, three frequency dividers, the inputs of which are connected to the output of the clock generator, four AND elements, two blocks of OR elements , two shift registers, two selectors, a NOT element and a trigger, the outputs of which are connected to the first inputs of the first and; second AND elements, the second inputs of which are connected to the first output of the RAM, and the outputs to control inputs of the first and second selectors, respectively, the information inputs of which are connected to the second output of the RAM, and the outputs to the inputs of the first and second blocks of the OR elements, whose outputs are connected to the information inputs of the first and second shift registers, respectively, of clock inputs connected to the output of the clock generator, the outputs of the shift registers are connected to the inputs of the second element OR, the output of which is connected to the information input of the video signal generator, the outputs of second, second, and third frequency dividers are connected respectively to the control input of the encoder and the first input of the third element AND, the first input of the fourth element AND and the control input of the synchronous generator, the second output of which is connected to the first input of the third element OR, and the third output to the second input the third OR element and the input of the zero setting of the read address counter, the output of the third OR element is connected to the second input of the third AND element, the NOT element input and the control input of the switch, the information inputs of which are connected to the outputs of the write address counter and the read address counter, the output of the third element I is connected to the summing input of the record address counter, the second input of the fourth element I is connected to the output of the element NOT, and the output is to the summed input of the reading address counter and the counting input of the trigger . 0 five 0 0 five Subscription