SU1368913A1 - Arrangement for presenting information of crt screen - Google Patents

Abstract

The invention relates to automation, control systems, computing and television equipment, and can be used in the production of graphic information on the screens of multi-purpose television video terminal devices. The purpose of the invention is to improve the accuracy of the device. To do this, selectors 7 and 8 codes, trigger I 2, elements 13 and 14 AND, blocks 1 6 and 17 of the OR element and I5 OR element and the corresponding functional connections are introduced into the device. The information is displayed on the CRT screens of television indicators by digitally shifting the image discretization elements in the horizontal direction according to the image configuration for intervals exceeding the resolution threshold between adjacent image discretization elements limited by the video transmission bandwidth of the CRT television indicators. 3 il. (L

Description

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The invention relates to automation, control systems, computing and television technology and can be used in the production of graphic information on the screens of multi-purpose television video terminal devices.

The purpose of the invention is to increase the accuracy of the device.

Figure 1 shows the functional diagram of the device; Fig. 2 illustrates an embodiment of the first (second) block of the OR elements for the case of a fourfold increase in the frequency generated by the clock generator to the horizontal sampling rate of the image; FIG. 3 is a fragment of an image on a CRT.

The device contains an operating memory unit 1 for recording and storing during regeneration of image points and shift codes in the horizontal direction, a reading address counter 2, a clock generator 3 required for generating a standard television synchro mix signal and OIG pulses, a driver 4 video signal intended for summation with a television sync signal and supplying a full iB video signal to a CRT modulator 5, a clock generator 6 performing the function of frequency processing, synchronized

rum 6 is greater than the horizontal sampling rate of the image.

The first 16 (second 17) block of elements OR contains elements OR 18 and 19, elements 3 OR 20 and 21, and element 4 OR 22.

The device works as follows.

The discretized image together with the shift codes of each image element at input 23 (informational) in accordance with the addresses at input 24 (address) is entered into

memory block 1. During the forward progress of the sweeps, the information from block 1 is read in the sequence of addresses generated by the counter 2, which is set to its initial state.

CGI pulses coming from the second output of the synchronizing generator 3 to the input Setting to O of counter 2. The reading frequency is fed to its (summing) counting input from the output of the 1I divider frequency

A dot in which the frequency is divided to the value of the frequency at which the pixels are displayed on the CRT screen (horizontal image sampling rate). The information bits counted from block 1, through the element And 13 or the element And 14, arrive at the information inputs of the selectors 7 and 8, respectively.

Channel One - Element I 13, Se

device, the value is 35–7, the block of 16 OR elements and the torus is much larger than the shift register frequency 9, and the second channel and horizontal image sampling, as well as the generation of the frequency of 2 mHz obtained from dividing the fundamental frequency, the first 7 and the second 8 code selectors required to feed the signal recorded in the memory cells of block 1 to the corresponding bits of the first 9 and second 10 shift registers, designed to divide the clock frequency of the shift, developed by generator 6 to the value of the horizontal frequency image scaling, as well as performing horizontal positioning of image points, frequency divider I1, decreasing frequencies from generator 6 to sampling frequency of memory cells, trigger 12, first 13 and second 14 And elements and OR 15 element, first 16 and second 17 blocks of OR elements, performing the function of expanding the information bits by as many times as the shift frequency produced by the AND element generator 14, the selector 8, the block 17 of the OR elements and the shift register 10, are organized for the purpose of alternating

their work in time when displaying a sequence of image sampling elements on the screen.

From even memory cells, information is entered into one shift register, with

odd - in another. Elements 13 and 14 are controlled by signals from the direct and inverse outputs of trigger 12, respectively, to the counting input of which the same frequency is applied as at

totalizing counter input 2.

The element OR 15 connects the outputs of the shift registers and delivers information to the information input of the imaging unit 4 of the video signal, which is summed up

with a full television sync mixture signal coming from sync generator 3 to its control input.

In accordance with the shift code, which is fed to the address inputs of the selectors from the second output of block I, the information bits are assigned to one of their outputs.

Consider the case where the frequency of the clock generator 6 is four times the horizontal sampling rate of the image.

A bit of information is selected on the selector and is fed to that input of a block of OR elements that corresponds to the desired shift of the image bit horizontally (Figure 2),

The bit of the image element is recorded in those bits of the shift register within its bit grid, which correspond to its specified shift on the CRT screen. So, the bit of information allocated at output 2 to the selector 15 of the CRT modulator, clock generator, the first output of which is connected to the input of the synchro generator, the second output of which is connected to the input. Setting the O address of the reading address counter to the detor is 20 frequency carrier, different for the shear (figure 2). The information bit is written to four consecutive shift register bits corresponding to the required shift.

e with the fact that, in order to ensure the accuracy of the device, it contains the first and second code selectors, the trigger, the first and second elements And, the first

image decomposition element due to the 25 th and second blocks of the OR elements,

the fact that in our case the frequency that goes to the control (clock) input of the shift register is four times higher than the horizontal sampling rate of the image.

At the output of the shift register, the duration of the image decomposition element is preserved as it would be if the decomposition elements of the image were directly supplied to the CRT with a frequency equal to the horizontal sampling frequency of the image.

In our case, this element of the image is shifted along the X axis by the required distance corresponding to the image configuration. I

The invention makes it possible to significantly increase the accuracy of displaying information on the CRT screens of television indicators by digitally shifting the image discretization elements in horizontal direction according to the image configuration at intervals that exceed the resolution threshold between adjacent image discretization elements limited by a strip

Claims (1)

transmission of video tracts of television indicators based on CRT. Invention Formula A device for displaying information on the screen of a cathode-ray tube (CRT) containing a memory unit, the address and information inputs of which are respectively the address and information inputs of the device, a synchronous generator, the first output of which is connected to the control input of the video signal generator that is connected to a CRT modulator, a clock generator, the first output of which is connected to the input of the synchronous generator, the second output of which is connected to the input Set in O of the reading address counter, so that, in order to improve the accuracy of the device, it contains the first and second code selectors, trigger, first and second elements AND, the first and second shift registers and the OR element, the output of which is connected to the information input of the video signal shaper, the inputs of the OR element are connected to the outputs of the first and second shift registers, information inputs to ohs are connected to the outputs of the first and second blocks of OR elements, the inputs of which are connected to the outputs of the first and second code selectors, whose information inputs are connected to the outputs of the first and second elements AND, one of the inputs of which are connected to the first output of the RAM, other inputs of the elements And connected respectively to the first and second outputs of the trigger, the counting input of which is connected to the output of the frequency divider connected to the counting input of the reading address counter, the input of the frequency divider is connected to the second in the output of the clock generator connected to the control inputs of the shift registers, the output of the reading address counter is connected to the control input of the RAM, the second output of which is connected to the address inputs of the code selectors. 0i / g. 2