SU1285521A1 - Device for generating graphic information on screen of television receiver - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in control devices for indicator devices. The purpose of the invention is to increase the quality of the image being formed by increasing the number of addressable points by obtaining a phase shift between adjacent brightness levels, which is achieved by introducing blocks 5 and 6 of the And elements, the third 9 and fourth 10 shift registers and the corresponding functional links, and also the execution of control block 2 as a combination of three elements HE 18, 19 and 20, four elements AND 14, 15, 16 and 17, phase 12 zero counter and phase 13 single one counter 13, which allows control of the position of each view pulse depending on the state of its discharge phase. 1 hp ff, 2 ill. with $

Description

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su cm

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1

1128552

The invention relates to automation and computing and can be used in control devices for indicator devices.

The aim of the invention is to improve the quality of the generated image by increasing the number of addressable points by obtaining a phase shift between adjacent luminance points.

ten

The synchronous generator 1 generates the television frequency and television sweep synchronization pulses, which are fed to the control unit 2 at the counting input of the 12 phase zero counter and at the counting input of the phase 13 counter of the unit through the HE 20. This allows the time counters 12 and 13 to separate phases with a time interval equal to the duration of the pulse of the clock frequency, since the change in the state of the output bits of the counter 12 of the phase zero occurs when the difference from zero to one of each pulse of the clock frequency. The change in the state of the 13 phase counter of the unit occurs when the difference from one to zero for each pulse of the clock hour

then you.

I

FIG. 1 is a functional diagram of the device; FIG. 2 is a timing diagram of the operation of the control unit j.

The device contains a synchronizer 1, the outputs of which are connected to the synchronization inputs of the control unit 2, the receiving register 3, unit 4 of the ele-20

NOT units, blocks 5 and 6 of the elements I, j to the outputs of the bits of the counters 12. the first 7 and the second 8, the third 9 and four phases are connected to the elements of the top 10 shift registers. Even -17 and NOT elements 18 and 19. The (or odd) bits of the registers 7, elements 14, 15 and 18 are named after the shift and 9 shift and the odd (or even) 25 pulses, which arrive at the inputs of the bits of the registers 8 and 10 shift soy-, dinene with outputs of blocks 5 and 6 elements And, respectively. The outputs of the shift registers are connected to the element OR 11.

The control unit 2 contains a 12 phase Zero counter, a 13 single phase counter, four AND 14-17 elements and three

item NOT 18-20. The element is NOT 20 ps, d- connected to the key to the counting input of the counter 1 ... output bits of the counter 13 phase

units, write pulses are extracted. Register 3 outputs (phase bits). connected to the inputs of the block 4 elements NOT and with one of the inputs of the block 6 ele40

thirty

write registers 7 and 8, respectively (Fig. 2). The lowest bit of the phase 12 counter 12 is fed to the input of the shift of the register 7, and through the element NOT 18 to the input of the register 8 of the shift-, as a result of which information is recorded with the phase zero and is shifted. On elements of both 16 and 17 and element

And, and the outputs of the block 4 elements are NOT connected to one of the inputs of the block 5 elements I. The outputs of the register 3 (spacing bits) are connected to other inputs of the blocks 5 and 6 elements I.

for registers 9 and 10, and the low order of counter 13 of the phase of the unit enters the input of register 9 of the shift and through the element NOT 19 to the input of the shift of the register 10, as a result of which the information is stored with the phase of the unit and its shift. .

Information read from RAM (not

Information read from RAM (not

The odd (even) outputs of the block 5, the ELE-45 is shown), enters the register 3, AND is connected to the information of the phase and is fed to one of the inputs of the block 6 of the elements AND and the inputs of the block 4 of the elements NOT, and the bits of the inputs the odd (even) register 8, and the even (odd) outputs of the block 5 I elements - to the information inputs of the even (odd) register - 50 ka 6 and to the input of the block 5 elements And, country 7. The odd (even) outputs of the block outputs block 4 elements are NOT supported; 6 elements are And are connected to the information inputs of the odd (even) register 10 and even (not nye) vykosti fed to other inputs bloklyuchony to one of the inputs of the block elements 5 bits Value I. phases logical zero or a unit prohibits

..

The moves of block 6 of the I elements - to information 55 permit the passage of bits of the matrices inputs of the even (odd) register 9.

The device works as follows.

luminances from the output of blocks 5 and 6 of the elements AND to the information inputs of the registers. Odd luminance bits are sent to odd registers 7 or

0

The clock generator 1 generates the clock frequency and synchronization pulses of the television scan, which are fed to the control unit 2 at the counting input of phase 12 counter zero and at the counting input of counter 13 phase units through the HE 20 element. This allows time division of the counters 12 and 13 s a time interval equal to the duration of the clock pulse, since a change in the state of the output bits of the counter 12 phase zero occurs at a difference from zero to one of each clock pulse. The change in the state of the 13 phase counter of the unit occurs when the difference from one to zero for each pulse of the clock hour

0

then you.

The j outputs of the bits of the 12-phase meters are connected to the inputs of the -17 elements and the HE elements 18 and 19. The elements 14, 15 and 18 are pulsed, which are fed to the inputs connected to the output bits of the phase counter 13

write registers 7 and 8, respectively (Fig. 2). The low-order bit of the phase 12 counter 12 is fed to the input of the shift of the register 7, and through the element NOT 18 to the input of the register 8 of the shift-, resulting in the recording of information with the phase zero and its shift. On elements of both 16 and 17 and element

units, write pulses are emitted

for registers 9 and 10, and the low order of counter 13 of the phase of the unit enters the input of register 9 of the shift and through the element NOT 19 to the input of the shift of the register 10, as a result of which the information is stored with the phase of the unit and its shift. .

Information read from RAM (not

shown), enters the register 3, the phase rows go to one of the inputs of block 6 AND elements and inputs of the block 4 elements NOT, and discharge 6 and to the input of block 5 elements AND, the outputs of block 4 elements NOT

the bones arrive at the other inputs of block 6 and at the input of block 5 of the elements I, the outputs of the block of 4 elements NOT

The keys are to one of the inputs of the block 5 elements I. The value of the phase bits of the logical zero or one prohibits

 permits the passage of bits

luminances from the output of blocks 5 and 6 of the elements AND to the information inputs of the registers. Odd luminance bits are sent to odd registers 7 or

3

Y, and even bits come to the chapters of registers 8 or 10, drone bits with a zero phase go to the information inputs of registers 7 and 8, and from a single phase to the inputs of registers 9 and 10.

The state of the phase bits of the logical zero or unit from the outputs of block 5 and 6 elements and commutes the passage of the brightness to the information inputs of the corresponding shift registers. The zero-phase brightness bits are fed to the information inputs of registers 7 and 8, and the single-phase bits, to the information inputs of registers 9 and 10.

From the output of registers 7-10, information is transmitted through the element OR 11 to the output of the device — to a television receiver (not shown).

In this way, the position of each video pulse is controlled depending on the state of its discharge phase, as a result of which the quality of the display of the sign of the graphic information on the television receiver is increased.

Claims (1)

1. A device for generating graphic information on a television receiver screen, comprising a receiving register whose input is an input of the device, a block of 35 HE elements, the first and second shift registers, the Shift and Recording inputs of which are connected to the first, second, third and the fourth output of the control unit, the output of which is the output of the device, is due to the fact that, in order to improve the quality of the formed image by increasing the number 40 2 The device according to claim 1, characterized in that the control unit comprises three NOT elements, four AND elements and phase zero and one counters, the installation inputs in O of which are interconnected, the installation input in 1 phase counter of the unit connected to the output of the first element NO The input of which is connected to the input of the installation in 1 phase zero counter, the first output of which is the first output of the block and is connected. with the first input of the first element AND and the input of the second element NOT, the second output is connected to the second input of the first element AND and the first input of the second element AND, the third output is connected to the third input of the first element AND and the second input of the second element And whose third input is connected With the output of the second element NOT, which is the second output of the block, the outputs of the first and second elements of AND are the third and fourth outputs of the block respectively, the first output of the phase counter of the unit is connected to the first input of the third element AND and the input ohm of the third element is NOT and is the sixth output of the block, the second output is connected to the second entry point by obtaining the phase of the third element And and the first input shift between adjacent luminance bits, it contains the first and second blocks of elements And the third and fourth shift registers, the outputs of the shift registers are connected to the inputs of the OR element, the inputs of the Shift and Record of the third and fourth shift registers are connected respectively to the fifth, sixth, seventh and eighth outputs of the control unit, infor-55 unit. . five 0 20 25 thirty 35 0 The main inputs of the first and second shift registers are connected to the output of the first block of And elements, the information inputs of the third and fourth shift registers are connected to the output of the second block of And elements, one of the inputs of the And block blocks is connected to the outputs of the first group of the receiving register, the outputs of the second group of which. pogo connected to other inputs of the second block of elements And and the inputs of the block of elements NOT, the output of which is connected to other inputs of the first block of elements I. 2 The device according to claim 1, characterized in that the control unit comprises three NOT elements, four AND elements and phase zero and one counters, the installation inputs in O of which are interconnected, the installation input in 1 phase counter of the unit connected to the output of the first element NO The input of which is connected to the input of the installation in 1 phase zero counter, the first output of which is the first output of the block and is connected. with the first input of the first element AND and the input of the second element NOT, the second output is connected to the second input of the first element AND and the first input of the second element AND, the third output is connected to the third input of the first element AND and the second input of the second element And whose third input is connected With the output of the second element NOT, which is the second output of the block, the outputs of the first and second elements of AND are the third and fourth outputs of the block respectively, the first output of the phase counter of the unit is connected to the first input of the third element AND and the input ohm of the third element is NOT and is the sixth output of the block, the second output is connected to the second input of the third element, And the first input do of the fourth element And, the third output is connected to the third input of the third element And and the second input of the fourth element And, the third input ko-. The torus is connected to the output of the third element NOT, which is the fifth, the output of the block, the outputs of the third and fourth elements of AND are the eighth and seventh outputs respectively. P and W.I17 P fcdg. Pr no. 7 playllg fcdS Pr nothing. eight ipp lll P Phase zero behind fg / g