SU976500A1 - Switching device - Google Patents

Description

one

The invention relates to electrical measuring equipment, in particular, to switches of measuring information systems,

The commutators of measuring signals are known, comprising switching units of input measuring channels and a switch control device. The input measuring signal switching unit combines an output channel group and is connected to a measuring device (analog-digital converter, digital voltmeter). The switch control device, respectively, contains counters and channel decoders for channel groups and channel sets, the generator of the channel polling frequency of channels 11 .

However, such switches provide a low rate of polling channels, especially when contact switching.

The closest to the proposed technical entity is a switch, containing M commutation commutation switchboards

signals, each of which is connected to the output of a group of N channels and a control device containing counters} vl channels in the group to M channel groups, the outputs of which are connected to the inputs of the decoder N channels in the ground and M groups of channels whose outputs are connected to switching inputs of the switchboards, which determines the choice of one particular switchboard and one

10 channels on it, a master oscillator, the output of Hbie pulses of which are fed to the counting input of the counter of N channels in the group when operating in cyclic mode and to the recording inputs of the counters N1 of the channels in

IS group and M rpymi channels when working in address mode | 2

However, the known device has an insufficient rate of polling channels

20 switches in address mode.

The purpose of the invention is to increase the speed of polling the switch channels in the address mode. The goal is achieved by three, that the switch containing the serially connected counter and the decoder of N channels in the group, the counter and the decoder of M channel groups, the master oscillator and the element AND of the addressing mode are entered in series by the counter and decoder P of the com- munication blocks, each of which contains M groups of channels, memorizing registers of S channels in the group according to the number R of blocks of the commutator S1I, P storing registers of the M groups of channels, storing the register P of the switching units, P elements And records, P elements Jl reset an wasp, P inverters and a time delay block, while storing the registers of M channels in a group, M groups of channels and P switching blocks are sequentially connected to the corresponding decoders, one inputs of the P elements And records are connected to each other and connected to the output of the time delay block, another input with one of the outputs of the decoder P switching units from 1nsch to P and the input of one of the P inverters, and outputs with recording inputs of the corresponding storage registers of M channels in a group and M groups of channels from 1 to R and P inputs of recording the registering register P of switching units; the outputs of the P inverters are connected to one input of the P elements of the reset, the other inputs of which are interconnected and connected to the bus of the Taoyot sign with the memory, and the outputs are connected to the reset inputs of the corresponding storage registers of N channels in the group and M channel groups from the 1st to the P and P inputs of the reset of the storage register P of the switching units, the output of the giving generator is connected to one input of the element AND of the addressing mode, the other input of which is connected to the bus of the indication of the address mode, and the output with union of the inputs of counters N recording channels in the group, and M channels. P switching blocks and the input of the time delay block. The drawing shows a functional diagram of the device. The device contains a master oscillator 1, the output clock of which is fed to the element And 2 coincide with the sign of the address mode, counters 3-5 K | channel numbers in the group, M channel groups and P blocks of the cooTBeTCTBeifflo communicators, having inputs for recording the code for the channel number in the group, channel group numbers and the switching unit number, decoders 6-8 Ы channel numbers in the M group of channel groups and P switching units, respectively, converting code received from the corresponding counters 3-5, storing registers 9-1-9-P, 10-1-10-P, 11 channel numbers in the group, M groups of channels by the number of switching blocks P and storing register P blocks of switching, VCB signals which are control signals switching on the keys of switchboards of a certain group, AND 12 1-12-Р entries, inverters 13-1-13-Р, elements Иt 14-1-14-Р reset, time delay block 15, which provides a delay of the clock pulses of the master oscillator 1, The proposed device works as follows, In the address. In the switch operation mode, counters 3-5 N channel numbers in the group, M channel groups and P switching units are set to the position corresponding to the specified address, selected manually or remotely. The recording signal in the address mode is generated by the clock clock 1 of the ls of the master oscillator 1 and through the element 21 it passes to the combination, the 1st inputs of the record of all counters 3-5. These counters, in the particular case, can be a single counter, the lower bits of which are intended to select the channel number in the group, the following to select the channel group number (switchboard number), and the older ones to select the number of the switching unit. A switching unit is a set of. Rpyim channels or M switchboards, such switching units can be P. Decoders 6-8 N channel numbers in the group, M channel groups and P switching units convert the code of the corresponding counters 3-5 into control signals to switch on the switch channels previously received ija entry memory registers 9-11. The device contains memory registers for storing the code of the selected channel number. The P registers 9-1-9-P are used to memorize the code of the channel number in group L. The P registers 10-1-10-P are used to memorize the code of the group number of channels M. One register 11 serves for memorizing the number of the switching unit P. From the register output, the control signals go directly to switching on the keys of the switchboards.

The record in the registers 9-1-9-P, iO-1-lOP and 11 is made according to the clock pulses of the master oscillator 1, passing through the time delay block 15. The time delay makes it possible to work on such device nodes as counters 3-5 and decoders 6-8 before writing the code to the register.

Recording pulses are passed to the recording inputs of registers 9-1-0-Р and 10-1-10-Р through recording elements 12-1-12-Р, which ensure that the clock pulses of the master oscillator 1 are passed only when there is a signal to select this switching unit. , one of the P blocks. These selection signals are the P output signals of the decoder P switching units, which are fed one at a time to the input of the And 12-1-12-P recording elements.

When selecting the appropriate switching unit, the recording signal at the output of one of the elements 12-1-12 of the record to the recording input of one of the registers of the N number of the channel in the group to one of the register-storing M channel groups corresponding to this selected switch unit R.

The storage register of the MI of the switching units has P write entries, since in this register the write to each bit is carried out independently - according to the output signal of one of the And 12-1-12-P recording elements.

Thus, when choosing any block of cohomat P at the output of registers, utflating signals of switching unit selection, channel groups in it and channel numbers in the group appear, which will determine the inclusion of a specific cache in this block.

The switch can work in two modes :, with memorization and without memorizing the switched on channel in one switching unit after switching to the selection of another unit of commutation.

In the no-memory mode, there is no external signal. Working with memory, which is fed to the inputs of the AND 14-1-14-P reset elements as a zero signal. With its absence at these inputs of the elements And 14-1-14-P reset - a single signal. The second inputs receive the inverted output signals of the 8 P decoder switching units from the output of the inverters 13-1-13-Р and when choosing this switching unit at the second input

the corresponding element AND 14-1-14-P reset appears a zero signal prohibiting the reset of registers. When switching to another switching unit P, this signal becomes single, since from the decoder P of switching units now a zero non-selection signal is received. At the second input of the AND 14-1-14-Р reset element, there is also a single one, corresponding to the absence of signals. Working with memory, and the output of the AND reset element is a zero register reset signal.

Thus, when switching to another switching unit P, the channel number register in group N and the channel group register M corresponding to the previously selected switching unit P are reset and the previously selected channel is turned off when the selection signal disappears,

The storage register of the MI of the switching unit has P reset inputs; since, similarly to the recording, the reset of each bgo bit is carried out independently by the output signals of the corresponding AND 14-1-14-P reset elements. When switching to another switching unit, the register bit And corresponding to the previously selected switching unit is also reset. In this mode, without memorizing, operation in the address mode occurs in the same way as a known device, only one channel is switched on at the same time.

In the memory mode, a single signal also appears at the second input of the AND 14-1-14-P reset element at the moment when the signal for selecting the high-voltage switching unit P disappears. But due to the presence of the signal, the Memory operation at the combined first inputs of the And elements 14- 1-14-P reset supports zero signal. It prohibits the occurrence of a register reset signal at the time of the loss of a signal.

When selecting a channel in each switching unit and recording it into the register of M channels in the group and the register M of channel groups, the corresponding switching unit P, the registers of all other switching units in which the channels have been selected are not reset, but. previously selected channels that are turned on until 4–4 rounds are selected in these switching units. channels.

This cut-off mode of operation with aapomania makes it possible to switch on one O1mento R channels by the number of blocks

JP switching from one control device containing a clock generator, counting and decoder channel numbers and recording registry

invention formula

A switch containing serially connected counters and a deitframer of channels in a group, a counter and a decoder of M channel groups, a master oscillator, and an AND address mode element, characterized in that, in order to increase the rate of polling channels in the address mode, sequentially connected counters and descramblers are introduced R / blocks of commutators, each of which contains M groups of channels, P storing registers of N channels in the group by the number R of switching units, R storing registers of M channels, storing the register P of switching units, R elements And records, P elements AND reset P inverters and a time delay block, while remembering the registers of the channels in the group, M groups of channels and P switching units are connected in series with the corresponding decoders, one input of the P elements And records are interconnected and connected with the output of the time delay unit, another input with one of the outputs of the decoder P blocks in the switching from 1st to P and the input of one of the P inverters, and outputs, with the recording inputs of the corresponding J / channel registers in the group and M groups of channels from l-ix to P and P by the inputs of the storage register P of switching units, the outputs of the inverters P are connected to one input of the P elements AND reset, the other inputs of which are combined, interconnected and connected to the bus of the characteristic Work with memory, and the outputs are connected to - reset inputs of the corresponding storage registers of N channels in the group and M groups of channels from 1st to P and P with reset inputs of the storage register P of the switching unit; the output of the master oscillator is connected to one input of the AND element of the address mode, the other input of which is connected to the bus when naka reZh11ma address, and the output from the combined inputs of the counters recording channels in the group N, M groups of P Jr switching units and an input of time delay unit channels.

Sources of information that are irrelevant to the examination

1 Dolgov V. A., Gonestas E. Yu. Switching devices of automatic control systems, M, Energie, 1969, p. 7O-74, rice, 47.5O,

2i Ish switchboard F7100. .TU-25-04-g46O-76 (prototype).

Claims (1)

claims decryptor decryptor generator The switch containing the channels connected in a group, the counter and the channel groups AND, specifying the AND element of the address mode, which means that, in order to increase the speed of channel polling in the address mode, the counter and decoder P are connected in series , switching blocks, each of which contains M groups of channels, P memory registers of N channels in a group according to the number of P switching blocks, P memory registers of M channel groups, memory register P of switching blocks, P elements AND records, P elements AND reset, P inverters and a time delay unit, while the storage registers of the channels in the group, M channel groups and P switching units are connected in series with the corresponding decoders, one of the inputs of the P elements and records are interconnected and connected to the output of the time delay unit, the other input with one of the outputs decipher <0 976500 8 radiators of P switching units from the 1st to P and the input of one of the P inverters, and the outputs, with the recording inputs of the corresponding memory registers For channels in the group and M groups of channels from the 1st to P and P memory recording inputs the register P of switching units, the outputs of the inverters P are connected to one input P of the reset elements AND, the other inputs of which are combined, connected to each other and connected to the attribute bus Memory operation, and the outputs are connected to the reset inputs of the corresponding memory registers of the N channels in the group and M groups channels from 1st to P and P input by resetting the memory register P of the switching units, the output of the master oscillator is connected to one input of the address mode element AND, the other input of which is connected to the address mode indicator bus, and the output with the combined recording inputs of the counters of N channels in the group, M groups of channels And P switching units and the input of the time delay block.