SU443486A1 - Decimal Pulse Counter - Google Patents

Description

one

The present invention relates to scaling circuits made on ferrite-semiconductor automation elements and electronics.

Known decimal pulse counters with adjustable conversion factor, made on the basis of successive shift registers.

However, the known counters are complex, since each decimal bit of it must consist of ten cells, while such successive circuits of large length have a low noise immunity.

In order to increase the reliability of the device, the outputs of the descrambler are connected to the pushing windings of the serial register and the windings of the recurrent register through the memory cells whose output is connected via its own delay line to its input, the recurrent register restart input is connected to its windings through the delay line, the output of the switch each higher bit is connected via the transfer unit to the inputs of the memory cell and the next lower bit transfer unit, and through the delay line - from the sub input switch of the subsequent lower bit, the outputs of all transfer units are connected directly to the coil of the cells of the sequential register and

through the delay line to the recording input of its first cell, and the output of the lower-order transfer unit is connected directly to the recording input of the first-order transfer unit, and through the delay line to the zero input of the switch of this bit.

The drawing shows the proposed device.

The decimal impulse counter contains a shift register 1, a switch 2 conversion factors, a transfer unit 3, a delay line 4-7, a decoder 8, a recurrent register 9, and a memory cell 10.

The device works as follows.

Using switches 2, the required conversion factor is set in decimal terms.

A separate device, not shown in the drawing, is used to prepare the meter for fuction. For this, for example, manually using a button, a single training impulse is recorded in the first cells of the sequential and recurrent shift registers 1 and 9, respectively, as well as in the transfer unit 3 and the memory cell 10 of the highest (left according to the scheme) bit. Further, all operations are automatically transferred to the system.

The pulses to be counted are fed to the counter input as readable to all cells of the recurrent register 9. The corresponding outputs of the decoder 8 successively appear pulses, the conversion factors of which with respect to the input are equal to: 10, ..., 10 100 (1 ).

At the output of the high-order memory cell 10, a signal appears that goes to the read windings of the cells of the sequential register 1, and since the preparation pulse is recorded in its first cell, the signal is shifted to its second cell. At the same time, the same signal arrives at the coil of the quenching of the recurrent register 9, resets all its cells to the zero state and rewrites its first cell through the delay line, which delays the write pulse for the time required to reliably quench the signals in all the cells of the recurrent register 9 In addition, from the output of memory cell 10, the preparation signal via delay line 5 is rewritten to its recording input.

Next, a series of input pulses again triggers the high-order memory cell 10, suppressing the recurrent register 9 and advancing the signal to the next (second) cell of the sequential register 1, while the signal from the output of this cell through the corresponding (second) input of switch 2 produces reading from the high-order transfer block 3. The signal from its output prepares for the triggering of a memory cell 10 of the next bit by recording a pulse at its input.

At the same time, the signal from the output of block 3 of the high-order non-transfer makes preparation for the next low-order operation by sending a signal to the recording input of the transfer unit of the discharge and extinguishing all the cells of the sequential register 1. Through the delay line 7, it prepares for the new operation (next dec Regularly register) 1 by writing a signal to its first cell.

The next cycle is that after passing to the input counter of the input pulses, the same operations are performed with the recurrent register 9 and the memory cell 10 of the next least significant bit, as described above. However, the switch of this bit is set to zero, so the signal from the output of transfer unit 3 passes through delay line 6 and the zero input of switch 2 and reads the signal from transfer unit 3 of the same bit. Thus, the shift of the conversion factor to one (second) bit is achieved.

The signal of the preparation is fed to the input of the recording of the memory cell 10 lower order, the arrival of each input pulse leads to the triggering of the memory cell 10 lower order (right according to the scheme), and through it

and to the advancement of signals on the cells of the sequential register 1 with the frequency of the following input nmnulsov.

At the moment of arrival of the fourth input pulse, the signal arrives at the output of the low-order transfer unit 3 and, therefore, at the output of the entire counter.

The signal at the output of the counter produces damping of pulses in all cells of memory 10 (except the high-order bit) and cells of the sequential register 1; in addition, it records the pulse of preparation in the transfer unit 3 of the first high-order bit, resulting in a counter prepared for account cycles.

Through the use of transfer units, memory cells and delay lines connected in a certain way to sequential and recurrent registers, it is possible to obtain any integer conversion rate of the counter in the range from 1 to 999 input pulses. As the number of counter bits increases by one, only a memory cell with a delay line and a transfer unit with a delay line are added to the device.

The length of the sequential register is constant and in the decimal system of counting is equal to 9. The length of the recurrent register is selected on the basis of the number of digits of the conversion factor.

Subject invention

A decimal pulse counter on ferrite semiconductor elements with an adjustable conversion factor, consisting of a recurrent shift register with an OOVi decoder and a serial shift register, the output of each cell of which is connected to the corresponding inputs of the decade conversion factor switches, characterized in that, to improve reliability, the outputs are decrypted with a conversion factor switch, characterized in that connected to the forward windings of the serial register and the windings of the recurrent register through the cells we, the output of which is connected n through its own delay line with its input, the re-start regnestr restart input is connected to its quench windings via the delay line, the output of the switch of each higher bit is connected via the transfer unit to the write inputs of the memory cell and the next lower level transfer unit, and delays - with a zero input of a switch of the next lower bit, the outputs of all transfer units are connected directly to the windings of the secondary register cell quenching and through the delay line - to the record input its first cell, and the output of the lower-order transfer unit is not connected. directly to the input of the record of the transfer unit of the first most significant bit, and through the zaderlski line - to the zero input of the switch of this bit.