SU432599A1 - FILLING DEVICE - Google Patents

Description

The field of application of the proposed device is digital information processing systems with sequential input and output of information. Known I-bit memory devices with sequential input / output of information containing address gate drivers, and read, write and read drivers, in which, for reducing the amount of equipment, one common for all bits of information extraction is used The readout memory is converted from a parallel form to a serial one by means of delay lines (LZ) connected at the outputs of each of the R read lines. At the same time, the delay time of each subsequent LZ increases linearly from bit to bit, thereby ensuring the Bozmohchkochno service of all R work bits with one block of information extraction in the time division mode. However, such a drawback has such drawbacks, such as the dependence of the maximum delay time of the LS on the number of bits and the need to use LPs with a small attenuation coefficient and wide bandwidth, which complicates the design of multi-bit memory. In order to simplify the storage of a device with one common block of information / information, it additionally introduces an Iltulse distributor, a trigger, an element “P, Switching schemes and key circuits. Moreover, the input “Circulation is connected to the installation input to the initial position of the single divisor and the installation input to“ 1 trigger. The input clock is connected to the input of the distributor and through the element "And, the other input of which is connected to the output of the trigger, with the inputs of the drivers of the address, write and read gate. The outputs of the distributor are connected to the control inputs of the respective switching circuits and to the control inputs of the key circuits. Bus "Device information input is connected to the input of the recording world record, the output of which is connected with the signal; the main inputs of the key circuits. In this case, RL with linearly increasing times, delays are excluded from the memory, and for each address selected, not one is fed as usual, but R oG rotations, where R is the number of working bits of the memory. Thus, the reproduction of stored information, as well as its recording, is performed sequentially in time, starting from the 1st and ending with R-bni, the working bit. The drawing shows a memory circuit including drive 1, synchronization unit 2, containing pulse distributor 3, trigger 4, element "And 5, form drives of address, write and read gates, respectively, 6, 7, 8; address control unit 9; the recording unit 10, consisting of one common bit generator shinti // and R key circuits 12; block connect 13; containing j switching circuits 14 and one common block-allocation of information 15.

The proposed memory works as follows.

The reference pulse sets the distributor 3 to the initial state, and the trigger 4 sets it to the state "1. In this case, at the control input of the element "AND 5, a permitting and potential appears. Under the action of clock pulses, the distributor 3 generates signals that control key and switching circuits corresponding to 12 and 14, and the formers of gates 6, 7, 8 form the corresponding address strobe and read or write gate, depending on the selected operating mode of the charger. Write or “Read. At the same time, for each clock emulation and operation, recording or reading information in only one of the working bits. After the clock imiuls, the write or read cycle is completed and the reset 4 is reset to the initial state, prohibiting the operation of the synchronization unit 2. After the address has been changed, a new circulation impulse is given and the entire cycle of the memory is repeated.

The information is entered by a serial code directly to the input.

of the common shaper zapggsi //, and the conclusion - with the release of the common shaper of the reader 15.

The amount of equipment of the proposed storage device without LZ is substantially smaller, compared to the known storage devices of this type with LZ. The gain in the equipment volume increases with the number of bits, since the complexity of the known memory devices with LZ is a non-linear function of the number of working bits.

Subject invention

Storage device containing accumulator, address gates, write and read shapers, write and read shapers, characterized in that, for the purpose of the device, a pulse distributor, trigger, element "P, comm mutation schemes and key elements circuits, the input bus “Circulation is connected to the installation input to the initial state of the distributor and the input device to the“ L trigger, the input clock bus is connected to the input of the distributor and through the element “I, whose other input Connected to the trigger output - with the inputs of the address gateway shaper, the readout and the outputs, the distributor outputs are connected to the control inputs of the corresponding switching circuits and control inputs, and the key circuits, the input device information input is connected to the input of the 1 front view forms, the output of which is connected to the key signal inputs.