SU1332383A1 - Serial-access buffer storage unit - Google Patents

Abstract

The invention is based on computing technology and can be used to build buffer software iykmySlLm k. -g- 9. - ". I - m Th: 4 “transmitting devices” in systems for collecting data transmission and processing, in particular, in devices for collecting information from digital sensors in telemetry systems. The purpose of the invention is to expand the functionality of the storage device by analyzing the input data and eliminating the recording in the drive of little-changing data. The device contains drive 1, registers 2–5 addresses, decoder 6, blocks of comparison 7–9, multiplexers 10, 11, adder 12, counter 13, reversible counter 14, trigger 15, delay elements 16, 17, And 18 elements 22, elements OR 23, 24 and elements NOT 25j 26. 1 np. i (L

Description

The invention relates to the field of computing and can be used in the construction of buffer storage devices in systems for collecting, transmitting and processing data, in particular in devices for collecting information QT digital sensors in telemetry systems.

The purpose of the invention is to expand the functionality of the storage device by analyzing the input dacha and excluding the recording in the drive, low-changing data.

The drawing shows a flowchart of a sequential buffer storage device.

The sequential buffer memory device contains the accumulator 1, the first 2, the second 3 and the third 4 registers, the fourth register 5 addresses, the decoder 6, the first 7, the second 8 and the third 9 comparison blocks, the first 10 and second 11 multiplexers, adder 12, counter 13, reversible counter 14, trigger 15, first 16 and second 17 delay elements, elements 18 and 22 of the first through fifth, first 23 and second 24 elements OR and the first 25 and second 26 elements NOT ”

The device works as follows.

Before operation, the registers, counters, and trigger 15 are reset. In this case, the And 21 element is blocked by a low logic level signal from the direct output of the trigger 15 ". At the same time, the high logic level signal at the first input of the And 22 element allows the recording clock to pass. The input information is transmitted by a parallel code simultaneously to the data inputs of register 4 and to the first inputs (A) of the comparison unit 9, which performs comparison with the code recorded in register 4 in the previous recording cycle and coming from its output to the second inputs (B) of the block 9. Comparison. If the code value on the first inputs (A) is greater than or equal to the code value on the second inputs (B), then a signal appears on the second output (A T) B of the comparison block 9 that goes to the second control inputs of the multiplexers 10 and 11 and switches them to such a state that the output of the first multiplexer 10 receives data from its first data input, and the code of the second multiplexer

ra 11 - data from its second data entry.

Thus, the first inputs (A) of the adder 12 are received through

multiplexer 10 input data in the direct code, to its second inputs (B) through the inverse output of the multiplexer

11- data from register 4 in the inverse-i-th code, and the third input (input of the adder's loan) is a logical one. The adder 12 subtracts from the number received at input A, the number received at input B according to the method of the second addition, which is implemented as follows. Adder 12 performs the addition of the number at the first (A) input, represented in the direct code, the number at the second (B) input, represented in the return code, and adds to the sum obtained the unit of the least significant bit that arrives at the third (Po) output loan As a result, the output of the adder 12 generates a number equal to the difference between the value of the input information and the number recorded in register 4 in the previous recording cycle .. 1

If the number at the input A of the comparison block 9 is less than the number entering the input B, then at its output A; A signal arrives at the first control inputs of the optical multiplexers 10 and 11 and switches them in such a way that the inputs A of the adder

12The number comes from register 4,

and the inputs B is the number from the input, the device data. Further, at the output of the adder, according to Wits, the difference of numbers is similar to that described, however, this will be the difference between the number recorded in register 4 in the previous recording cycle and the number found at 1Ms at the input of the device. Thus, at the outputs of the adder 12, a number is formed, which is the modulus of the difference of the specified numbers, which is fed to the second inputs A of the second comparison unit 8. On the third inputs This block receives a number from the input of the device increment code. Comparison unit 8 compares the numbers at inputs A and B and, if A B, a signal appears at the output (A: B) of the block and allows the recording time to pass through the AND 22 element, the second OR element 24 to the synchronous register 5 addresses that forms but

- .3

A new address for recording the input word.

In addition, the sync pulse from the output of the second element OR 24 through the delay element 17 is fed to the synchronization input of register 2, while the information from the input of register 4 is rewritten to the main, and the state of the counter 13 to the additional bits of the storage cell 1. Through the first and second the delay elements 16 and 17, the write clock signal is input to the Reset Counter 13, zero it, and register clock 4, and the information present at the device input will be written to the register.

Further recording of incoming information is similar.

If, starting from any moment of time, the input information remains unchanged or its change in absolute value does not exceed the value of the number of information increment code specified at the inputs, then, having come to the device input for the first time, with the arrival of the next recording clock, it is written to register 4 then block 8 comparison, comparing the information values at inputs A and B, will establish fact AB and at the input of the block (AB) a low-level signal will appear and, blocking element I 22 will prohibit the passage of subsequent sync write pulse to the clock, the address register 5, and other device components.

The logic zero level, the input to the element HE 26f is inverted and allows the write clock to pass through the element AND 19, the first element OR 23 to the counting input of the binary counter 13, which counts the number of cycles of repeating information.

As soon as the input information changes to such an extent that the absolute value of the difference between the input information and the number in register 4 exceeds the increment code value, the signal from the input of the comparison unit 8 by the level of logical unit will allow the write clock to pass through the first element 22 to the device nodes and prohibit its passage to the synchronous signal. counter 13 through the second element And 19, since at its input will arrive the level of logical zero from the output of the element 20

32383.

NOT 26. From the output of the AND 22 element, the write clock through the second element OR 24 is fed to the counting input of the register 5 of the address, where a new address is formed to write the number to the accumulator. A write clock pulse through delay element 17 enters the sync-input register 2 and information from register 4 will be overwritten into the main ones, and the state of counter 13 into additional bits of the memory cell of drive 1. From the input of the delay element 17, the write clock pulses go to the input of the element 16, the delay, the ac of its output to the input Reset the counter 13, swaddled it, and to the synchronous input of the register 4, recording new information in it.

If the absolute value of the difference between the input information and information in the 4th number register is zero or does not exceed the value specified on the device increment code inputs, 25 and the number of write cycles is such that the counter 13 under the influence of multiple clock pulses reaches its final state — on the outputs all its bits are set to-, with logical units, the element AND 18 opens and at its output a level of logical unit appears, which, arriving at the input A. In the second comparison unit 8, causes the appearance of its output signal is a logical unit. This signal blocks AND 19 and opens AND 22, with the result that the subsequent write clock through AND 22 and OR 24 enters the counting input of address register 5, which forms a new address for recording the word input.

Next, the device records information from the outputs of register 4 to the main ones, and the states of counter 13 to additional bits of cell 1 as described, after which the information presently present at the inputs of the device is overwritten in register 4, and counter 13 is reset.

Further recording of information received at the input of the device is similar.

The clock sync pulse recording, by step (step 5 on the register of the 5 address, also goes to the first input +1 of the invert counter 14, increasing

0

five

0

five

l1

most of its contents are at one. When all accumulator cells are filled, which corresponds to the achievement of counter 14 of its final state, the signal from the first output of the reversible counter, acting on the S input trigger 15, triggers its switching, as a result of which the inverted output of the trigger is set to a zero zero, and on the forward, the logical unit, thereby blocking the element And 22, and opening the element And 21, preparing the device for operation in the read mode.

Information is read from the device as follows.

When reading information from an external device, sync pulses are sent to the read input, each of which corresponds to one clock cycle of the output information. Information is read on the rising edge of the read pulse. If the additional bits of accumulator 1 contain zeros, i.e. the information during the recording did not repeat, the high logic level signal appears at the output of the first block 7 of the comparison (counter 13 is zeroed before operation), allowing the clock to pass through the AND 21 element to the second input -1 of the reversing counter 15 and the OR 24 element; and through the latter, to the counting input of the register 5 of the address, which, on the leading edge of the pulse, forms the address of the accumulator cell 1. At each clock cycle, the information on the next order of the memory cell of the accumulator 1 is read.

If any value is recorded in the next cell in the additional bits, then the output of the first block 7 of the comparison has a logical zero level, the element 21 will be blocked, the read pulses do not pass to the counting input of the address 5 register. The level of logical zero from the output of the first comparison unit 7 inverts with the element NOT 25, thus opening the element AND 20, through which the transmitting pulses go to the first element OR 23, and from it to the counting input of the counter 13. Clock counter the read sync pulses continue until the value of counter-7 coincides with the value recorded in the additional bits of the memory cell of accumulator 1. With a combination of 32383

In the event of a fall, the operation continues as described, the signal from the output of the element OR 24 resets the counter 13.

Each read sync pulse arriving at the second input -1 of the reversing counter 14 reduces its content by one. When reading

The Q information from the last cell of the accumulator, counter 14, is zeroed out (the state of a logical zero on all outputs of the counter), as a result of which the second output of the counter B shows a signal that switches the trigger 15 to the zero state, while the inverse output the trigger is set to a single level, and on the forward level — zero.

2Q At the same time, the And 21 element is blocked by a low logic level signal, and further operation of the device in the read mode is stopped. Simultaneously, the logical level

25 units from the inverse output of the trigger 15 are fed to the input of the element And 22,. preparing the device for recording.

Claims (1)

Invention Formula 30 Serial buffer storage device containing a drive, information input and output of which are connected respectively to the output of the first register and to the input 35 of the second register, the first output of which is the device data output, the first data input of the first register is connected to the third register output, whose data input is the device data input, the third register synchronization input is connected to the counter reset input and to the output of the first delay element whose input is connected to the output of the second 45 delay elements and to the synchronous input of the First Register, the second data input of which is connected to the output of the counter, to the input of the first element Nick to the first input of the first comparison unit, 5Q, the second input of which is connected to the output of the second register, the clock input of the counter is connected to the output of the first OR element, the first and second inputs of which are connected respectively 55 to the outputs of the second and third elements And, the first input of which is e-, with BxofliOM reading the device and connected to the first input of the fourth element And, the second input of which 7, connected to the output of the first comparison block and to the input of the first element NOT, the output of which is connected to the second input of the third element AND, the third input of the fourth element AND is connected to the forward output of the trigger, the inverse output of which is connected to the first input of the fifth element AND, the second input of which connected to the selector of the second comparison unit and to the input of the second element NOT, the output of which is connected to the first input of the second element AND, the second input of which is the recording input of the device and connected to the third input of the fifth element Which is connected to the addition input of the reversible counter and to the first input of the second OR element, the second input of which is connected to the output of the fourth AND element and to the subtraction input of the reversible counter, the output of the second OR element is connected to the input of the second delay element and the address register input, the output of which is connected to the input of the decoder, the output of which is connected to the address inputs of the accumulator, the first and second outputs of the reversible counter are connected respectively to the inputs of the installation and reset the trigger, the component S. Schustenk about, Editor L. Gratilo Tehred L. Serdyukova Proofreader C, Shekmar Order 3839/48 Circulation 589 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d. A / 5 Production and printing company, Uzhgorod, st. Project, 4 323838 the stroke of the first element I is connected to the first input of the second comparison unit, characterized in that, in order to expand the functionality of the device by analyzing the input data and excluding writing to the drive with little-changing data, it contains the third unit 10 comparison, the first and second multiplexers and the adder, the output of which is connected to the second input of the second comparison unit, the third input of the generator is the input of the increment code 5 devices, the first and second inputs of the data adder are connected to the high-voltage signals of the first and inverse outputs of the second multiplexer, the first and second control inputs of which are connected respectively to the first and second outputs of the third comparison unit, the first input of which is connected to the first data inputs of the first and second multiplexers and to 25 data input of the third register, the outputs of which are connected to the second input of the third brilliance of the comparison, to the second data inputs of the first and second multiplexers, the transfer input 0 adder connected to the input unit of the device.