SU1116426A1 - Device for searching numbers in given range - Google Patents

Abstract

A device for searching the number of numbers in a specified range, containing an input register register, a frequency center register, a clock generator, a grouping node, a higher decade clock node, a logical analysis unit, and an OR element, and the input of the input numbers register is connected to the information input of the device , the input of the center of the range register is connected to the device input, the output of the logical analysis unit is connected to the first input of the OR element, the input of the clock generator is connected to the device start input, and the output is to the inputs of the grouping node. bits and node of the highest decade clock selection, differing in that, in order to improve speed, the device contains a clock distributor, a second logical analysis block, a trigger and two groups of NOT elements, while the logical analysis block contains groups of elements AND, groups of elements SH , the zero decoder, adder, register, three flip-flops, two AND elements, the OR element and the NOT element, while the output of the clock generator is connected to the input of the clock distributor, the output of the clock selection node The signals are connected to the trigger input of the trigger, the output of which is the output of the device, and the information input is connected to the output of the element, the second input of which is connected to the output of the second logic analysis unit, the output of the clock generator is connected to the inputs of the shift control of the input number register and the center range register, the outputs of the lower decades of which are connected to the inputs of the elements NOT respectively the first and second groups, the first inputs of the elements AND the first groups of the first and second blocks of logical analysis, connect The first inputs of elements 2 and the second groups of the first and second blocks of logical analysis are connected to the outputs of elements NOT the second and first groups, respectively, in each logical analysis block the outputs of the first and second elements groups of nodes to the first inputs of the elements OR of the first and second groups, respectively, whose outputs are connected to the inputs of the first and second groups of the adder, the outputs of which bits are connected to the information inputs meters of the register, the outputs of the bits of which are connected to the information inputs of the zero decoder and the first inputs of the AND elements of the third group, whose outputs are connected to the second inputs of the OR elements of the second group, the first output of the clock distributor connects it to the second inputs of the AND elements

Description

second and second groups, with clock inputs of the first and second triggers and with the first input of the OR element of the first and second logical analysis, the second output of the clock distributor is connected to the second inputs of the OR elements of the first group, the second inputs of the AND elements of the third group and the first input of the first element Both the first and second blocks of logical analysis, the third output of the clock distributor and the output of the group of bits of the bits of the scraper: respectively to the first and second control inputs of the decoders zero first o and the second logical analysis block, the device start input is connected to the zeroing inputs of the first and second triggers of the first and second

6426

logical analysis blocks, while in each logical analysis block the overflow output of the adder is connected to the information inputs of the first and third triggers, the output of the first trigger is connected to the transfer input of the adder and to the input of the element NOT whose output is connected to the first input of the second element I, whose output is the output of this logical analysis unit, and the second input is connected to the output of the second trigger, whose information input is connected to the output of the decoder zero, the output .. of the third trigger is adapted to the second one the course of the first element, AND, the output of which is connected to the second input of the IS element, the output of which is connected to the control input of the register.

The invention relates to computing technology: can be used in devices for processing digital radar information.

A device is known for searching for numbers in a given range, comprising registers of numbers, comparison blocks, triggers, and a register of values of the limits of the range C I -5.

Disadvantages- ; said device consists in its complexity and low speed.

Closest to the proposed device for searching numbers in a given range, containing registers, clock generator, clock generators, AND, OR, NOT, triggers, decoder, adder, and shift register 2.

However, this device has insufficient performance.

The purpose of the invention is to increase the speed, device,

The goal is achieved by the fact that a device for searching numbers in a given range, containing a register of input numbers, a center-range register, a clock generator, a grouping node, a high-decade clock selection node, a logical analysis unit, and an OR element, with the input of a number input register to the information input of the device, the input of the register of the center of the range is connected to the master input of the device, the output of the logical analysis unit is connected to the first input of the SHS element, the input of the clock pulse generator connected to the device startup input, and the output to the inputs of the bit grouping node and the clock selection node of the highest decade, a clock distributor, a second logic analysis block, a trigger and two groups of NOT elements are entered, each logic analysis block contains groups And elements, groups of elements Ш1И, decoder zero, adder, register, three triggers, two elements И, element ШИИ and element NOT, while the output of the clock generator is connected; to the input of the clock distributor, the output of the node of the clock with The decade is connected to the trigger input of the trigger, the output of which is the output of the device, and the information input is connected to the output of the OR element, the second input of which is connected to the output of the second logical analysis unit, the output of the clock generator is connected to the inputs of the register of input numbers and the center of the range, the outputs of the lower decades of which are connected to the inputs of the elements NOT of the first and second groups respectively, the first inputs of the elements of the first, the groups of the first and second blocks of logical analysis The first inputs of the elements of the second groups of the first and second logical analysis blocks are connected to the outputs of the elements of the second and the first groups, respectively, in each block of the logical analysis of the output elements the first and second groups are connected to the first inputs of the OR elements of the first and second groups, respectively, the outputs of which are connected to the inputs of the first and second groups of the adder, the outputs of which are connected to the information inputs am of the register, whose bit outputs are connected to the information inputs of the zero decoder and the first inputs of elements AND of the third group, whose outputs are connected to the second inputs of the OR elements of the second group, the first output of the clock pulse distributor and the second inputs of the first and second elements, with the clock inputs of the first and second triggers and with the first input of the OR element of the first and second blocks of logical analysis, the second output of the clock distributor is connected to the second inputs of the SHSh elements of the first g rup py, the second inputs of the third group elements and the first input of the first element and the first and second logic analysis blocks, the third output of the clock distributor and the output of the bit grouping node are connected respectively to the first and second control inputs of the decoders zero of the first and second logic blocks analysis, the device start input is connected to the zeroing inputs of the first and second triggers of the first and second logic analysis blocks, with the overflow output in each logic analysis block The ora is connected to the information inputs of the first and third triggers, the output of the first trigger is connected to the transfer totalizer and to the input of the element NOT whose output is connected to the first input of the second element AND whose output is the output of this logical analysis unit, and the second input is connected to the output of the second trigger, the information input of which is connected to the output of the decoder zero, the output of the third trigger is connected to the second input of the first element And the output of which is connected to the second input of the shsh element, the output of which is Linked to the control input of the register. FIG. I is a block diagram of a device for searching for numbers in a given range; on figt. block diagram of a logical analysis flea. The device contains a register of 1 input numbers, a register 2 of the center of the range, a group of elements NOT 3 and 4, blocks 5 and 6 of logical analysis, an element OR 7, a trigger 8, a generator of 9 clock pulses, a distributor of 10 clock pulses, a node AND group and a node 12 of clock selection older decade. Blocks 5 and 6 of the logical analysis contain groups of elements AND 13, 14 and 15, groups of elements OR 16 and 17, triggers 18 and 19, adder 20, trigger 21, register 22, decoder 23 zero, element NOT 24, elements 25 25, element SHSh 27. The device has information input 28, assignments input 29, start input 30. Elok 5 (6) has inputs 3137. The device works as follows. Binary-decimal number A is entered into register 2 — the center of the range; binary 1-decimal numbers X, which are to be analyzed, are entered into register 1 in turn. When the input into register 1 of each successive number is completed, an input pulse is given to the input of the device start; This pulse sets in the initial state the triggers 19 and 18 of the blocks 5 (6) of the logical analysis and starts the generator of 9 clock pulses forming the series of clock pulses. the layer of clock pulses corresponds to the number, de °° of input binary-decimal numbers. Starting from the younger decades, the numbers from registers 1 and 2 begin to arrive at the inputs 31 and 32 of blocks 5 and 6 of ogical analysis. The belonging of numbers backwards, anno1. The range is determined by a decadal calculation of the difference between the input numbers X and the number A (the center of the range) with simultaneous analysis of the resulting difference. If the difference in absolute value does not exceed half of the specified search range, then the analyzed number is read into the belonging range. Since it is not known in advance which number A or X is greater, there are two blocks of 5 and 6 logical analysis operating in parallel in the device. In block 5, subtraction XA is made, in block 6, AX is calculated, and each of these differences is analyzed simultaneously. When subtracting the last older decades of numbers A and X of one hundred. Novits knows which of these two numbers is greater, and the analysis of both difference values ends at the same time. The result of the analysis is removed from the output of that of blocks 5 or 6, in which the subtraction of a smaller number from a greater number was performed. . Through the element OR 7, the pulse of the highlight decade node 12 of the highest decade is recorded in three germs 8, where it is stored until the end of the analysis of the next X number. The output of the triple 8 is the output of the device. Each of blocks 5 and 6 of the logical analysis produces a decade subtraction of incoming binary numbers 31 and 32 binary numbers with simultaneous analysis of the difference obtained. To simplify the understanding of the flowcharts of FIG. 1 and FIG. The 2 links, over which the decade is transmitted by a parallel four-bit code, are indicated by thick arrows.

For each decade, blocks 5.6 operate in three clocks. According to the tact T (|, coming from the distributor 10

clock pulses to the inputs of 34 blocks, optionally, the value of the search range

5 and 6, the groups of elements are determined by the number of 13 and 14, black numbers which, in parallel, the senior decades, are grouped by a narrow four-digit adder 20, the next decade of subtracted

numbers On the trailing edge of the cycle T., 50 at the time T is checked on the past through the element OR 27, a decade. Lyuba spoils the writing of the unadjusted unit in the higher bits of the code.

Decades of difference in four-bit differences will trigger the trigger register 22. At the same time, the set-P will disappear and exit to the state corresponding to cnrk5Se of the signal analysis unit belonging to the transfer output of the adder 20,.

trigger 19 transfer to the next deca- If in MOMeat the subtraction of the last

do and trigger 21 | frrektsii., the highest decade of the difference occurs

in the older decades of the difference code.

The number of units tested for the senior decades and, the sledol, are 11 groups. For each of. grouped cycles of the highest decade lio clock T, received from the distributor of 10 clock pulses to the inputs 35 of blocks 5 and 6,. the resulting decade of difference is corrected. To do this, one of the inputs of the adder 20 through the group of elements AND 15 to the group of elements OR 17 connects an uncorrected decade of difference from the output of the register 22, and to another input of the adder 20 through the group of elements OR 16, a clock pulse T is applied, thus ensuring the existence of this input the adder 20 of the parallel correction code 1010 (ten). If at this time the correction trigger 21 gives the correction command, i.e. the correction is necessary, the element I 25 is open, and on the back edge of the pulse TQ, which passed through the circuit element 25, the element. OR 27, the corrected value of this decade of difference is written to register 22. According to the tact T, coming from the distributor 10 to the input 36 of blocks 5 and 6, the obtained decade difference is analyzed. The analysis of the difference between the numbers A and X is based on the fact that the magnitude of the difference can be judged by the presence of units in the senior decades of the difference. For example, if the numbers contain four decades, and there is no one difference in the two senior decades, the difference can not exceed 99 (code 0000 0000 1001 1001), which in this case will exceed half the number search range for any given number A.- .. the center of the range exceeding the number 99. Thus, the task of determining whether a number belongs to a range is reduced to checking the presence of all zeros, a signal about the need for a loan from the next decade, this will indicate that this analysis block produced the subtraction more th number of the smaller. In this case, the Era bathes the element NOT 24, the element AND 26 is closed, this analysis block is turned off, the result is found from another analysis block. On the backfront of the highest decade pulse coming from the output of node 12, the result of the analysis is recorded in the trigger 8 and arrives at the output of the device. The technical and economic advantages of the predictable device as compared to the known ones are manifested in the fact that it is possible to analyze the difference in the device sequentially at the same time as the process of its calculation, due to which the speed of the device is improved.

Claims (1)

A DEVICE FOR SEARCHING NUMBERS IN A PRESENT RANGE, containing an input numbers register, a center. Range register, a clock pulse generator, a grouping unit, a senior decade clock allocation unit, a logical analysis unit and an OR element, the input numbers register input being connected to the device information input, the input range center register is connected to the master input of the device,. the output of the logical analysis unit is connected to the first input of the OR element, the input of the clock generator is connected to the start input of the device, and the output to the inputs of the grouping unit. bits and node of the selection of the beat of the senior decade, characterized in that, in order to improve performance, the device contains a clock pulse distributor, a second logical analysis unit, a trigger and two groups of elements NOT, with each logical analysis block contains groups of elements AND, groups of elements OR, zero decoder, adder, register, three triggers, two AND elements, • OR element and NOT element, while the output of the clock generator is connected to the input of the clock distributor, the output of the clock selection node is old It has been connected for decades to the trigger input of the trigger, the output of which is the output of the device, and the information input is connected to the output of the CPU element, the second input of which is connected to the output of the second logical analysis unit, the output of the clock generator is connected to the inputs for controlling the shift of the input numbers register and the center of the range register , the outputs of the younger 'decades of which are connected to the inputs of the elements NOT respectively of the first and second groups, the first inputs of the elements AND of the first groups of the first and second blocks of logical analysis, conn the outputs of the lower decades of the register of input numbers and the register of the center of the range, respectively, the first inputs of the elements of the second groups of the first and second logical analysis blocks are connected to the outputs of the NOT elements of the second and first groups, respectively, in each logical analysis block the outputs of the elements of the first and second groups nodes - * are connected to the first inputs of the OR elements of the first and second groups, respectively, the outputs of which are connected to the inputs of the first and second groups of the adder, the outputs of the discharges of which are connected to the information inputs of istra outputs bits which are connected to the data inputs of zero decoder and the first inputs of AND gates of the third group, which outputs are connected to second inputs of the OR elements of the second group, the first output clock distributor Cpd-t nen with the second inputs of the elements, and per- " None * | VAZ * 4 * LF of the second and second groups, with clock inputs of the first and second triggers and with the first input of the OR element of the first and second logical analysis, the second output of the clock distributor is connected to the second "inputs of the OR elements of the first group, the second inputs of the AND elements of the third group and the first the input of the first element And the first and second blocks of logical analysis, the third output of the clock distributor and the output of the group of discharge grouping are shodly, respectively, to the first and second control inputs of the zero decoders first of the second and second logical analysis blocks, the device start input is connected to the zeroing inputs of the first and second triggers of the first and second logical analysis blocks, while in each logical analysis block, the adder overflow output is connected to the information inputs of the first and third triggers, the output of the first trigger is connected to the transfer input • of the adder and to the input of the element NOT, the output of which is connected to the first input of the second element AND, the output of which is the output of this logical analysis unit, and the second input is connected output of the second flip-flop having an information input coupled to an output of zero decoder, a third flip-flop output being connected to the second input of the first AND gate whose output is connected to a second input of OR gate whose output is connected to the control input of the register.