SU1397968A1 - Buffer storage - Google Patents

Abstract

The invention relates to computing and can be used in data transmission and reception systems, in particular, in the processing of information from subscribers in the order of its receipt. The aim of the invention is to increase the reliability of the operation of the device. The device contains a memory block, an address counter, a number register, first and second comparison blocks, a repetition counter, a pulse distributor, a trigger, AND, OR, NAND, delay elements. The purpose of the invention is achieved by recording at each address of the accumulator a control code of the number of device cycles with the same information at the inputs. When reading, the control code goes to one input of the comparison unit, the other inputs of which are connected to the outputs of the counter-repetition. In the case of incomparison, the operation of the address counter is blocked and the increment of the repetition counter up to the moment of comparison is allowed. As a result, the information on the output of the device remains unchanged for the time specified by the control code. 1 il. cl

Description

00

f

-sj

with

05 00

The invention relates to computing and can: be used in data transmission and reception systems, in particular, in processing information from subscribers in the order of its receipt.

The aim of the invention is to increase the reliability of the operation of the device.

The drawing shows a block diagram of a storage device.

The device contains a drive 1, a write block 2, a read block 3, an address counter 4, a decoder 5, equalization blocks 6 and 6j, a repetition counter 7, elements AND 8, -84, elements OR 9, and 9, element 10, register 11 numbers, trigger 12, elements 13, and 13 delays, AND-NOT element 14 input entry 15, input 16 readout, information inputs 17 and outputs 18. Blocks 1,2,3 and 5 are combined in memory block 19, and elements 8, and 10 in the distributor 20 pulses.

As trigger 12, RS-triggers or counting triggers can be used. In the first case, the S-input of the trigger must be connected to the output of the element And 8, and the R-input - with the output of the second delay element 13. If a counting trigger is used, the S-input must be connected to the output of the AND 8 element, and the clock input to the output of the second delay element 13J.

The device works as follows.

Before operation, counter 4, register 11, counter 7 and trigger 12 are zeroed out. At the output of trigger 12 - a high logic level. The input information is transmitted by a parallel code simultaneously to the information inputs of the input register 11 and to the inputs of the second comparison unit 6. The second comparison unit 6j compares the information recorded in the input register of the 11th number in the previous recording cycle with the information that appeared on the device inputs to the arrival of the subsequent recording clock. In the event that the subsequent recording cycle of information at the device inputs changes in at least one code sequence, the high logical level from the output of the second block 6 allows the passage of a sync pulse through

0

five

0

five

0

five

0

five

0

five

the first element AND 8 ,, the second element OR 9 on the counting input of the counter 4 addresses, which forms a new address for recording the word of input information. In addition, the clock sync pulse from the output of the second element OR 9 through the first element 13, the delays go to the synchronization input of block 2 of the record, while the information from the outputs of the register of the 11th number is copied to the main ones, and the readings of the counter 7 to the additional bits of the storage cell 1 Through the first 13 and second 13 delay elements, the write clock arrives at the Reset input of counter 7, thereby swaddling it, and the register synchronizes the 11th number, and the information present at that moment at the device inputs will be written to the register. Further recording of new code combinations is similar.

If, starting from a certain point in time, the input information remains unchanged for several recording cycles, then, having appeared at the inputs of the device for the first time with the arrival of the next recording clock, it will be recorded in the 11th register, after which the second comparison unit 6 with a low signal the logical level from its output, blocking the first element I 8, will prohibit the passage of subsequent sync pulses of the recording to the counting input of the counter 4 addresses and other nodes of the device.

The lower logical level at the output of the second comparison unit 6 is inverted by the AND-NOT element 14. A high logical level from its output unlocks the second element AND 8, so that the recording clock through the first element OR 9 goes to the counting input of the repeat counter 7, which counts the number cycles of repeating information, and the first input of the trigger 12, switching it to one state. At the same time, a low logic level is set at the output of the trigger.

As soon as the input information changes, by the arrival of the write clock, the second comparison unit 6 with a high logic level signal from its output will allow the write clock to pass through the first And 8 element to the device nodes, simultaneously allowing the write clock to pass to the counting input of the counter 7, since the device element AND will be opened by a high logic level signal arriving at its second input from the output of the AND-14 element. Under the influence of this sync pulse, the contents of counter 7 increase is one. From the output of the first element And the 8 ' sync pulse, via the element g1PI 92, arrives at the counting input of the 4 address counter, where the address for recording the repeated code nation is formed. In addition, after some EFFECT, determined by the first element 13, the delays, the same sync pulse will go to block 2 of the record, while the information from the output of the 11th register of the number is copied to the main ones, and the readings of the counter 7 to the additional bits of the memory cell 1 The record clock, which is even more delayed by the second delay element 13, arrives at the second input of the trigger 12, returning it to the initial state (high logic level at the output), at the input Reset of the repetition counter 7, thereby resetting it, and register 11 numbers. In this case, new information is written to the register. The delay time cG and cG, to which the first 13 and second 13 delay elements are set, respectively, must be chosen based on the fact that you first need to form an address at which information is written, then, after the end of transients in the address register, rewrite into a drive having the main and additional bits of the memory cells, information from the register of the 11th number and the counter 7 of the repetition, then reset the counter and write to the input register the new information.

Information is read from the device as follows. Sync pulses are received from the external device, each of which corresponds to one clock cycle of the output information. Information is read on the rising edge of the read pulse. If in additional bits of accumulator 1 zeros are written, m, e. the information is not repeated, then at the output of the first block 6,

a high logic level signal (counter 7 is zeroed before operation), allowing the passage of read sync pulses through the fourth element AND 8 and the second element OR 9 to the counting input of the address counter 4, which forms the cell address on the leading edge of the read pulse

drive, In each clock cycle, information is read from the next memory cell of drive 1.

If the next cell contains some value in the additional bits, then at the output of the first block 6, the comparison is low, the fourth element And 84 will be blocked, the read pulses will not be able to arrive.

The counting input counter 4 addresses. Low logic level from the output of the first block 6, the comparison is inverted by the element NOT 10, thereby unlocking the third element AND 8, through

which read pulses go to the first element OR 9, and from it to the counting input of counter 7, the clock clock count continues until the moment of coincidence

the value of counter 7 with the value recorded in the additional bits of the memory cell of accumulator 1. If it coincides, the operation continues as described, the signal from the output of the second element OR 9 will reset

counter 7.

f

Claims (1)

Invention Formula Buffer memory 40 contains a register of numbers whose information inputs are the same inputs of the device and connected to the inputs of the first group of the second comparison unit, the inputs of the second group 45 of which are connected to the outputs of the register of the number and to the inputs of the information bits of the memory block, the inputs of the service bits of which are connected to the outputs of the repetition counter and to the inputs of the first group of the first blocks Comparisons, the inputs of the second group of which are connected to the outputs of the service bits of the memory block, the outputs of the information bits of which are connected gg information outputs of the device, and the address inputs are connected to the outputs of the address counter, the sync input of which is connected to the output of the second OR element and to the output of the first delay element whose output is connected to the recording input of the memory unit and to the input of the second delay element whose output is connected to the synchronous input of the number register and to the reset input of the repetition counter, the synchronous input of which is connected to the output of the first OR element, whose inputs are connected respectively to the output of the second element of the first distributor output mpulsov, the pulse input of which is input to the read device and a control input the input of which is connected to the first input of the second element I and is the recording input of the device, the second input of the first element I is connected to the output of the second comparison unit, which is characterized by the fact that, in order to increase the reliability of the operation of the device, -NO, the trigger inputs are connected respectively with the output of the second element And with the output of the second delay element, the inverse trigger output under and the second output is connected corresponding to the 5th input to the first input of the element but with the output of the first comparison unit and with the first input of the second element OR, the second input of which is connected to the output of the first element AND, the first Editor L.Gratillo Compiled by O. Isaev Tehred M. Dykyk Order 2273/50 Circulation 590 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 I-IE, the second input and output of which are connected respectively with the output of the second comparison unit and with the second input of the second element I. Proofreader M. Demchik Subscription