SU1226528A1 - Buffer storage - Google Patents

Abstract

The invention relates to the field of computer technology, in particular to storage devices, and can be used in information collection and transmission systems of automated control systems for various technological processes. The purpose of the invention is to increase the reliability of the device. The device contains registers, a drive, triggers, AND elements, a multi-phase single pulse generator, an OR element, a switch, and counters. The device allows locking of the read mode during the write cycle and vice versa. 1 il. with s

Description

The invention relates to storage devices and can be used in information collection and transmission systems of automated control systems for various technological processes.

The purpose of the invention is to increase the reliability of the device.

The drawing shows a functional diagram of the buffer storage device.

The device contains the first register 1, drive 2, the second register 3, the first RS flip-flop 4, the first 5, the second 6, the third 7 And elements, the third RS-flip-flop 8, the multi-phase generator .9 single pulses, the second RS-flip-flop 10, element OR L, switch 12, the first counter 13, the second counter 14.

The device works as follows.

In the initial state, the address counters of write 13 and read 14, as well as the RS flip-flops 4 and 10 are reset, and the RS flip-flop 8. is in the single state. The drive 2 is in read mode.

At the appearance of a write pulse, the input information is recorded in the input register 1 and cocked at the B input of the RS flip-flop 4 into one state. Since the RS flip-flop 8 is in the single state, then through the first element I 5 the read-write signal goes to the 8-input of the RS flip-flop 10 and cocks it, which causes the drive 2 to switch from the read mode to the write mode, switch the switch 12 to the switching mode of the address of the output code of the counter 13 of the write address to the address inputs of the accumulator 2 and to the start of the multiphase generator 9 single, pulses in the mode of generation of write clock pulses, which appear sequentially on the first, second and third outputs for the clock The cycle of writing the next information word from the input register 1 to the drive 2. The first clock pulse records information from the input register 1 to the drive 2. The second pulse, the incoming q of the second output of the multiphase generator 9, has a single pulse - the address of the write address per unit .. Impulse appearance at the third output

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multi-phase generator 9 single 1-spools leads to the presence of high levels at both inputs of the second element And 6 and as a result - to reset the RS TpHrrepa 4 by R-EX. At. This occurrence of a high signal at its inverse output leads to resetting the RS flip-flop 10 to the zero state, and this switches the drive 2 to the read mode, switch 12 to the switching mode of the outputs of the read address counter 14 to the address inputs of the drive 2, and (ib. t5. clock pulses t5. cycle recording multiphase generator 9 single pulses.

ten

35

The appearance of a read pulse on the E: -input of the RS flip-flop 8 flips

20 it is in the zero state, thereby prohibiting the inclusion of the write mode until the cycle of reading information from accumulator 2 to the output register 3 ends.

25 an inverse output of the RS flip-flop B appears a single signal, which, due to the presence of a single level at the inverse output of the RS flip-flop 10, flows through the third element And 7 on

30 second control input of a multi-phase generator 9 single pulses, which allows the formation of pulses clocking the information reading cycle from accumulator 2 into the output register 3. At the beginning, a pulse appears at the fourth output of the multi-phase generator 9 single pulses entering through the OR element 11 to the second control input of accumulator 2. This pulse is used to read information from the zero memory cell of accumulator 2. Then, when a pulse appears, on P. NAC output of a multiphase generator 9 single pulses rewrite information at the output of accumulator 2 into output register 3. The appearance of a pulse at the sixth output of a multiphase generator 9 single impulses leads to an increase in the readout address by one, and the last impulse to the S-input coerces the RS flip-flop 8 into a single state , which results in the appearance of a signal accompanying the signal, turning off

55 multiphase generator 9 single pulses and the resolution to enable the recording mode H4 to the second input of the first element AND 5.

40

45

50

five

The appearance of a read pulse on the E: -input of the RS flip-flop 8 flips

0 it is in the zero state, thereby prohibiting the inclusion of a write mode until the cycle of reading information from accumulator 2 to the output register 3 ends. At the same time,

The 5 inverse output of the RS flip-flop B appears a single signal, which, due to the presence of a single level at the inverse output of the RS flip-flop 10, enters through the third element And 7 on

0 second control input of a multi-phase generator 9 single pulses, which allows the formation of pulses clocking the information reading cycle from drive 2 into the output register 3. At the beginning, a pulse appears at the fourth output of the multi-phase generator 9 single pulses entering through the OR element 11 to the second control input of accumulator 2. This pulse is used to read information from the zero memory cell of accumulator 2. Then, when a pulse appears, on P. NAC output of a multiphase generator 9 of the single pulses, the information on the output of accumulator 2 is copied to the output register 3. The appearance of a pulse at the sixth output of the multiphase generator 9 of single pulses leads to an increase in the readout address by one, and the last pulse to the S-input brings the RS flip-flop 8 to one state , which results in the appearance of a signal accompanying the signal, turning off

5 multiphase generator 9 single pulses and the resolution to enable the recording mode H4 to the second input of the first element AND 5.

0

five

0

In the event that the write pulse arrives at the time when the read cycle is not completed, the second input of the first element And 5 is blocked from activating the write mode of the RS flip-flop 10.

Similarly, in the case of the arrival of a read pulse during a time when the write cycle to drive 2 has not yet completed, blocking the activation of the read mode on the first input of the third element And 7 is completed until the end of the write cycle.

Claims (1)

Invention Formula The buffer memory containing the accumulator, the first and second registers, the first and second counters, the first, second and third triggers, elements AND, the information inputs of the first register being information inputs of the device, the outputs of the first register are connected to information inputs of the accumulator, the outputs of which connected to the information inputs of the second register, the outputs of which are the information outputs of the device, the first inputs of the first and third triggers are the control inputs of the device, tlichayuschees in that, for the purpose ponyyeni reliability of the device, it introduced a multiphase single pulse generator, a switch, an OR gate, the first input of the first flip-flop ten 15 20 25 thirty 35 connected to the control input of the first register, the inverse output of the first trigger is connected to one input of the second trigger, the other input of which is connected to the output of the first element I, the first input of which is connected to the first output of the first tripler and the first input of the second element (And, the output of which is connected to the second input of the first trigger, direct output The second trigger is connected to the control input of the switch and the first control inputs of the accumulator and the multiphase generator of single pulses, the second control input of which is connected to the output of the third element I, the first input of which is connected to the inverse output of the second trigger, and the second input to the inverse output of the third the trigger, the direct output of which is connected to the second input of the first element I and is the control output of the device, the outputs of the multiphase single pulse generator are connected respectively to the first input of the OR element, the input of the first counter, the second input of the second element AND, the second input of the OR element, the control input of the second register, the input of the second counter, the second input of the third trigger, the output of the OR element connected to the second control input of the accumulator, the address inputs of which are connected with the switch outputs, the inputs of the first and second groups of which are connected respectively to the outputs of the first and second counters. four lHuia sharpening 1 in your cvumiSanta