SU1388951A1 - Buffer storage device - Google Patents

Abstract

The invention relates to computing and can be used to accumulate discrete information in the order it arrives from communication channels or from other subscribers. The purpose of the invention is to expand the field of application of the device by blocking the recording when the drive is full. The device writes data to memory block 12 at the addresses generated by counter 8, and reads data from block 12 to addresses ipv ipvemy by counter 9. The write (read) pulse from input 15 (16) enters through And 1 (2 ) on trigger 4 (5), set it to one state. In addition, the write signal is increased, and the read signal is reduced by the state of the reversible counter 10. The outputs of counter 10 are connected to the element OR-NOT 3, the output of which goes to triggers 6 and 7. Resetting the counter 10 in a write cycle means that the block 12 overflows that prohibits the next write cycle by setting the trigger 6 to one state. Resetting the counter 10 in the reading cycle means emptying the block 12, which prohibits the next reading by setting the trigger 7 to the single state. The multiplexer 11 switches the outputs of the counters 8 and 9 to the address inputs of the block 12. 1 Il. (L

Description

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The invention relates to computing and can be used as a storage device in the processing of information in the order received from subscribers, for example, in a computer.

The purpose of the invention is to expand the field of application of the device by blocking the recording of data when the memory is full.

The drawing shows a block diagram of the device.

The device contains elements AND 1 and 2, element OR-NOT 3, triggers 4-7, counters 8 and 9, reversible counter 10, multiplexer II, memory block 12, information inputs 13, information outputs 14, recording input 15, input 16 read, synchronization input 17, write response signal output 18 and read response signal output 19.

The conversion factors for counters 8-10 are the same.

The device works as follows.

In the initial state, trigger 7 is set, and triggers 4-b, counters 8-10 are reset. The writing and reading processes are synchronized by clock signals from period-55 inputs and outputs of which are respectively information inputs and information outputs of the device, the first and second elements AND, the first inputs of which are respectively a recording input and a reading input of the device, a multiplexer, the first and second information the inputs of which are connected to the outputs of the first and second counters, respectively, the output of the multiplexer is connected to the address input of the memory unit, the counting input of the first counter is connected to nversnomu exit

the house of repetition of pulses equal to the duration of the recording time in memory block 12.

When a write pulse arrives at input 15, it passes through AND 1 and is written to trigger 4. In this case, trigger 7 is reset, the contents of counter 10, indicating the number of words in memory block 12, are increased, and the signal "Record the signal is blocked

Actually, the information inputs and information outputs of the device, the first and second elements are AND, the first inputs of which are respectively the recording input and the reading input of the device, the multiplexer, the first and second information inputs of which are connected to the outputs of the first and second counters respectively, the output of the multiplexer is connected to the address input memory unit, the counting input of the first counter is connected to the inverse output

reading through the AND 2 element, a 3S response of the first trigger is issued, to the input of the addition a reverse write response signal to the output. Thereafter, the recording input signal at input 15 is removed.

The zero signal at input 15 is written to trigger 4. This stops the write mode in memory block 12, increases the contents of counter 8, which now indicates the address of the next write cycle to the drive, unlocks the read signal through element 2, removes the signal from output 18 .

If the reversible counter 10 is reset (as a result of the complete filling of the memory block 12), a trigger 6 is set, which blocks the recording signal from passing through the And 1.

This is where the write cycle ends.

When a reading pulse arrives at 16, a number reading cycle occurs at the address determined by counter 9. The reading cycle is similar to the write cycle. By the end of the reading cycle, the contents of counter 9 are incremented by one, the contents of counter 10 are reduced by one, trigger 6 is reset, trigger 7 is set or reset, depending on the contents of counter 10.

40

a digital counter and to the second input of the second element I, the output of which is connected to the information input of the second trigger, the direct output of which is the output of the read response signal of the device, the counting input of the second counter connected to the inverse output of the second trigger to the control input of the multiplexer subtracting the reversible counter and to the second input of the first element C, the output of which

45 is connected to the information input of the first trigger, the direct output of which is the output of the recording response signal of the device, the clock input of the first trigger is connected to the clock input of the second trigger and is the input of clock pulses

50 devices, the outputs of the reversible counter are connected to the inputs of the OR-NOT element, characterized in that, in order to expand the field of application of the device by blocking data recording during memory overflow, it contains the third and fourth triggers, the outputs of which are connected to the third inputs of the first and the second element And, informational inputs of the third and fourth triggers

With simultaneous receipt of write and read pulses due to the fact that triggers 4 and 5 operate on different fronts of clock pulses, the first one changes its state, for example, trigger 4. In this case, the write cycle occurs and is blocked until the end of the write cycle on trigger 5. At the end of the write cycle, the read signal passes through the element 2 and sets the trigger 5. A read cycle occurs. This ensures that the write and read requests are serviced at the same time as they are received simultaneously.

Blocking a write or read from a memory block with an appropriately filled or empty drive expands the area of use of the device and eliminates the possibility of losing or reading false information.

Claims (1)

Invention Formula Buffer memory containing information block Actually, the information inputs and information outputs of the device, the first and second elements are AND, the first inputs of which are respectively the recording input and the reading input of the device, the multiplexer, the first and second information inputs of which are connected to the outputs of the first and second counters, the output of the multiplexer is connected to the address input memory unit, the counting input of the first counter is connected to the inverse output 0 a digital counter and to the second input of the second element I, the output of which is connected to the information input of the second trigger, the direct output of which is the output of the read response signal of the device, the counting input of the second counter connected to the inverse output of the second trigger to the control input of the multiplexer subtracting the reversible counter and to the second input of the first element C, the output of which 5 is connected to the information input of the first trigger, the direct output of which is the output of the recording response signal of the device, the clock input of the first trigger is connected to the clock input of the second trigger and is the input of clock pulses 0 devices, the outputs of the reversible counter are connected to the inputs of the element OR NOT, characterized in that, in order to expand the field of application of the device by blocking the data recording during memory overflow, it contains the third and fourth triggers, the outputs of which are connected to the third inputs of the first and the second element And, the information inputs of the third and fourth triggers 1388951 34 It is connected to the output of the OR-NOT element, clockwise the first and second triggers, the inputs of the third and fourth triggers of the sub mode of the memory unit are connected to the inverse of the inverse outputs of the corresponding output of the first trigger.