SU1695314A1 - Device for entry of information - Google Patents

Abstract

The invention relates to computing technology, in particular to devices for interfacing subscribers with a digital computer, and can be used in control digital computing systems. The aim of the invention is to expand the functionality by providing diagnostic testing of the device as part of digital computing systems and increasing their noise immunity. For this purpose, a device containing a control unit, a shift register, an address decoder, an amplifier group, a group of keys, n groups of separation elements and n switch groups of received words, two multiplexers, a buffer memory block, a cyclic address generator and a shift memory block are entered . 2 hp ff, 6 ill. J

Description

The invention relates to computing technology, in particular to devices for interfacing subscribers with a digital computer, and can be used in control digital computing systems.

The aim of the invention is to expand the functionality of the device by providing diagnostic testing-as part of digital computing systems and increasing their noise immunity.

Figure 1 shows the structural diagram of the device; FIG. 2 is a functional block diagram of the control unit; FIG. 3 is a functional block diagram of a cyclic address generator; figure 4-6 - time diagrams of the device in different modes.

The device for inputting information contains (Fig. 1) control block 1, cyclic address driver 2, block 3 of buffer memory, shift register 4, address decoder 5, amplifier group 6, key group 7, n groups of separation elements 8, n groups of switches 9 accepted words. The inputs of the amplifiers 6 through the elements 8 and the switches 9 are connected to the outputs of the keys 7, the inputs of which are connected to the outputs of the decoder 5, the information input 10 of which is connected to the first output 11 of the driver 2. The output 12 of the higher digit of the register 4 is connected to the information output 13 of the device , the input 14 of the mode of the register 4 is connected to the first output 15 of the control unit 1 Information input 16 of the register 4 is connected to the output of the unit 3, the access permission input 17 of which is connected to the second output 18 of the control unit 1, the inputs from the first to the seventh 19-25 which are connected sootOs

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It is valid with the following device inputs: synchronization input 26, initial installation input 27, clock input 28, address input 29, first, second and third enable inputs 30-32. The device also contains the first and second multiplexers 33 and 34. At the same time, the input 27 of the initial installation of the device is connected to the reset input 35 of the driver 2 and the reset input of the register 4 / clock input 28 and the device sync input 26 are connected respectively to the clock input 37 and input 38 synchronization of the driver 2. The second output 39 of the driver 2 is connected to the enable input 40 of the decoder 5 and the fourth permission input 41 of the control unit 1, the third output 42 of the driver 2 is connected to the input 43 of the operation of unit 1, the third, fourth and fifth outputs Odes 44-46 of which are connected respectively with the first and second control inputs 47 and 48 of the first multiplexer 33 and the control input 49 of the second multiplexer 34. The first information input 50 of the multiplexer 34 is connected to the output 11 of the imager 2, the second information input 51 of the multiplexer 34 is connected to address 29 of the device, and its output is connected to the address input 52 of block 3, the recording input 53 of which is connected to the first output 15 of block 1. Information input 54 of block 3 is connected to the output of the first multiplexer 33, the first, second and third inputs Dips 55-57 of which are connected respectively to the outputs of amplifiers of group 6, decoder 5, information output 58 of register 4, input 59 of the first digit of register 4 are connected to information input 60 of the device, clock input 61 of register 4 - with the sixth output 62 of unit 1. Output the shift memory unit 63 is connected to the information input 64 of the former 2.

Unit 1 is designed to form at its outputs 18, 44, 45, 46, 62 and 15 signals controlling the operation of the device.

An example implementation of the control unit 1 is depicted in FIG. When this input 19 synchronization and input 20 of the initial installation of block 1 is connected respectively to the first and second inputs 65 and 66 of the first element OR 67, the clock input 21 of the block is connected to the enable input 68 of the first decoder 69, the first inputs 70 and 71 of the first and second elements And 72 and 73, the first permitting input 74 of the second decoder 75. Address input 22 of unit 1 is connected to information inputs 76 and 77 of the first and third decoder 69 and 78, the first authorizing input 23 of the unit is connected to the first input 79 of the third element I 80, the second permitting input 24 b eye 1 is connected to the second input 81 of the first AND gate 72, the third enable

input 25 - with the first input 82 of the fourth element I 83, the fourth allowing input 41 of block 1 - with the second allowing input 84 of the second decoder 75, the input of operation 43 of block 1 is connected to information input 85 of the second decoder 75, the first output 15 of block 1 is connected to the second input 86 of the second element And 73 and the output of the third element And 80. The second output 18 of unit 1 is connected to the output of the second element OR 87, the third output 44 of unit 1 is connected to the third (inverse) enabling input 88 of the second decoder 75 and the output of the first trigger 89 The fourth output 45 block 1 soy Inonii yield vtoro0 th flip-flop 90, a fifth output 46 of block 1 soe- union of the fourth (inverted) enabling input 91 of the second decryptor 75, the second inputs 92 and 93 of third and fourth AND gates 80 and 83, the first

5 by the input 94 of the third element OR 95 and the output of the fourth element OR 96. The sixth output 62 of unit 1 is connected to the output of the first Element OR 97, the first input 98 of which is connected to the output of the first element AND 72,

0 the second input 99 to the first input 100 of the second element OR 87 and the output of the second element AND 73. The second and third inputs 101 and 102 of the second element OR 87 are connected respectively to the output of the second decoder

5 75 and the output of the fourth element And 83, the third input 103 of the first element And 72 is connected to the output of the third element OR 95, the second input 104 of which is connected to the first output 105 of the third decoder 78.

0 The second output 106 of the decoder 78 is connected to the inputs of the fourth element OR 96. The third input 107 of the first element OR 67 is connected to the first output 108 of the first decoder 69, the second 109 and the third 110

5 outputs of which are connected respectively to the installation inputs 111 and 112 of the first and second triggers 89 and 90, the reset inputs 113 and 114 of which are connected to the output of the first element OR 67.

0 The cyclic driver 2, shown in FIG. 3, contains a counter 115, an AND element 116, a trigger 117 and a delay element 118. The input 35 of the cyclic driver 2 is connected to the input 119

5 reset the counter 115 and the reset input 120 of the trigger 117. The input 37 of the driver 2 is connected to the counting input 121 of the counter 115 and through the element 118 delay - with the first input 122 of the element And 116, the input 38 of the driver 2 is connected to the input 123 of the record

the counter 115, and the input 64-syntactic input 124 of the counter 115, the first output 11 of the driver 2 is connected to the output 125 of the higher bits of the counter 115, the second output 39 - with the output of the trigger 117. The third exit 42 of the driver 2 is connected to the output 126 of the lower bits the counter 115, the overflow output 127 (the nth digit) of which is connected to the setup input 128 of the trigger 117, the second input 129 of the reset of which is connected to the output of the AND element 116, the second input 130 of which is connected to the output 131 of the j-ro discharge of the counter 115.

The shaper 2 is intended for sequential modification in the loop of the control digital computing complex (UCEM) of binary codes, which enter the inputs of the decoder 5 input relay words.

The block 3 of the buffer. Memory serves for recording and storing information of input relay words with the subsequent issuance of it through register 4 in the UTCM

Amplifiers 6 and switches 7 provide galvanic isolation of the device from controlled contacts (switches) 9 relays.

The separation elements 8 perform the function of INSTALLING OR, which provides a parallel compaction of the input relay words entered into the device.

Multiplexers 33 and 34 allow diagnostic testing of the device as part of the control PPM.

The multiplexer 33, depending on the code applied to its control inputs 47 and 48, provides a connection to the information input 54 of the block 3 or the outputs of the amplifiers (code 00), or the outputs of the decoder 5 (code 01), or outputs of the register 4 (code 10) ,

The multiplexer 34, depending on the value of the signal at its control input 49, provides a connection to the address input 52 of block 3, or the outputs 11 of the driver 2 (code 0), or the address input 29 of the device (code 1).

Block 63 is designed to tie 2 binary codes at the input 64, so when using the device in the redundant UCCM structure, the moments of recording the corresponding input relay words in blocks 3 in different channels are shifted relative to each other

The device operates in one of four self-contained modes, diagnostics of the 4-shift register, diagnostics of polling addresses of input relay words, unit 3 diagnostics.

The operation modes of the device are controlled by a control digital computer that outputs to the device input 29 a set of addresses in binary code. From the entire array of addresses coming from UCVM, the device recognizes the following:

a set of addresses for accessing the computer to block 3 - a;

address to start diagnosing addresses of input relay words - ft:

the start address of the diagnostics unit 3 - y;

address address UCUM to register.4 - (t,

address reset diagnostic modes - q.

In autonomous mode, the device operates as follows.

If the control digital computer does not access the device, the latter sequentially performs autonomous recording of input relay word information (information about the state of the relay contacts: O - open, 1 - closed) in block 3, and each input relay word corresponds to a certain memory cell unit 3. In one cycle of the control digital computer (the period of the synchronization signal at the input 26 of the device), all input relay words of the subscriber are recorded.

Recording information input relay words is as follows. When the device's power is turned on, input 27 receives a signal, the initial installation, which, at the input 20 of unit 1, at input 35 of the driver 2 and at input 36 of register 4, sets them to the initial state. At the same time, from outputs 44, 45 and 46 of block 1 to inputs 47 and 48 of multiplexer 33 and input

49 multiplexer 34 receives control signals of low level, which ensures switching the outputs of amplifiers 6 to

information input 54 of block 3, and signals from output 11 of driver 2 through inputs

50 multiplexer 33 is fed to the address input 52 of unit 3. Unit 1 outputs from output 15 to input 53 of unit 3 a low level signal,

by which the latter goes into the mode of recording information of input relay words.

At the end of the signal. The initial installation at the inputs 26 and 28 of the device begins to continuously receive signals of synchronization and ticks. According to the synchronization signal at the input 38 and the clock signal at the input 37 of the driver 2, the latter performs the initial setting at the output

11 binary address code. At the end of the synchronization signal, the address code, coming from the output 11 of the driver 2 to the input 10 of the decoder 5, begins to be periodically modified, with each

The address code corresponds to a high level at one of the outputs of the decoder 5. When the address code from output 39 of the driver 2 is modified, input 40 of the decoder 5 receives a control signal that determines the duration of the address at the outputs of the decoder 5. A high signal from one of the decoder 5 outputs enters one of the inputs of the corresponding | Key 7 and opens it, which leads to the appearance of a potential on the corresponding address bus of the input relay word. This potential through the closed contacts (switches) 9 and elements 8 is fed to the inputs of amplifiers b of the input relay word, and to the closed contacts 9 corresponds to the presence of potential at the inputs of amplifiers b, to open contacts - its absence.

To record the information of the input word in block 3, input 17 receives an appeal signal. This signal is generated at output 18 of block 1 using signals from outputs 39 and 42 of generator 2, to inputs 41 and 43 of block 1. The duration of the conversion signal is equal to the duration of the clock signal at input 21 of block 1,

To read the information of input relay words through the output 13 of the device into the control digital computer, the latter outputs to the device input 29 a read address code, which is the memory cell address of unit 3, followed by two control signals (at inputs 30 and 31 of the device). Upon arrival of the reading address to the input 22 of block 1, the latter generates a high-level control signal at output 46, in the presence of which multiplexer 34 passes the read address code through input 51 to address input 52 of block 3.

The control signal at the input 23 of block 1 generates a high level signal at the output 15, which is fed to the input 53 of block 3. At the same time, block 1 outputs signals 18 and 62 on which information from the output of block 3 is written to register 4. - e of this at the input 24 of block 1 from the digital computer receives a control signal. Using this signal, block 1 generates at the input 61 of the register 4 a series of shift pulses, according to which the output from the output 12 of the register 4 occurs with a serial code to the control digital computer.

During the reading of information from block 3 in the UDCM, the device does not cyclically record the information of the input relay words, since the read address a prohibits the formation of the output 18 of the block

1 signal Reversal when writing. Thus, the Read Turn signal has priority over the Write Turn signal. To read information from the next memory location of block 3, the control digital computer modifies the read address code at device input 29, and the read cycle repeats.

The diagnostics mode of register 4 consists in recording and reading from it diagnostic information of the control digital computer. When writing information to the device input 29, an address code is entered for this mode, followed by a serial information code at input 59 of register 4 and a control signal at input 31 of the device. On the control signal at input 24 of block 1, the last produces at the input 61 of register 4 a series of shift pulses, according to which the information of the control digital computer through the input 60 of the device is recorded with a serial code into the register 4. The diagnostic information from register 4 in the UHEC is read by the same control signals that when recording zero information, at which the contents of register 4 are output to the SCLC.

The diagnostics mode of addresses of input relay words consists in recording the state of the outputs of the decoder 5 in block 3 at the moments of recording the information of the corresponding input relay words and then reading the information in the SCLC. To organize this mode, information is recorded and read into block 3, which is formed in the same way as offline, while input 55 of multiplexer 33 is connected to input 54 of block 3 and input 56 is connected. To switch multiplexer 33 to input 29 of the device, the address code ft of this mode is received which is stored by block 1 and through output 45 is supplied as a signal (high level) to the input 48 of multiplexer 33.

The mode is reset either by the Initial setting signal, or by the synchronization signal (input 19 of block 1), or by the address code at input 29 of the device.

The diagnostics mode of unit 3 is performed by writing diagnostic information of the CLE to it, as well as reading diagnostic information at the CLE, and the write and read address codes that come into the device from the CLE correspond to the address codes of the diagnosed memory cells of block 3.

The recording of diagnostic information in block 3 is as follows From

In the digital computer, the address code of this mode, which is stored by block 1, arrives at the device input 29. At the same time, a high level signal is received from the output 44 to the input 47 of the multiplexer 33. The latter commutes the signal from the output 58 of register 4 through the input 57 of the multiplexer 33 to the input 55 of unit 3.

According to one of the address codes, sequential recording of the diagnostic information of the UHAC in register 4 takes place and after that it is overwritten in block 3 by the control signal U of the digital computer, which is fed to the input 32 of the device. Upon the arrival of the control signal at the input 25 of the unit 1, the latter generates at the output 18 an access signal of the unit 3, which is currently in recording mode (low level at the input 53). Thus, the contents of register 4 are recorded in the memory cell of block 3.

The reading of diagnostic information from block 3 occurs in the same way as reading information from input relay words in offline mode. The end of this diagnostic mode is analogous to resetting the diagnostics mode of the addresses of input relay words. After the output of the diagnostic information from the device, the control digital computer begins its processing by comparing the incoming information with the reference information stored in the UHAC memory. A full comparison of the diagnostic information with the reference standards indicates the operability of the tested device nodes.

Block 63 is a set of jumpers connecting the corresponding inputs 64 of driver 2 with buses of logical zero or logical one. In this case, a different code is entered in each channel. As a result, the moments of recording information of each relay word in different channels of the reserved set are shifted relative to each other. If a single electromagnetic interference occurs, information in block 3 of one channel may be distorted.

The overall sequence diagram (timing diagram) of the operation of the device is presented in Fig. 4.

In control unit 1, the decoder 69 serves to form from the address codes y and / 8, coming from the UHCW, high-level signals, cocking the flip-flops 89 and 90, which store, respectively, the diagnostic test modes of the block 3 and the diagnostic check of the addresses of the input relay words.

The decoder 75 is designed to form a signal. Circulation during the cyclic recording of input relay words in block 3.

The OR 67 element clears the flip-flops 89 and 90 via one of the Initial Setup or Synchronization signals, as well as a single signal generated by the decoder 69 from the binary code of the q address from the UDCM.

The element OR 95 is designed to receive a high-level control signal when the UHAC is accessing block 3 on any binary code of address set a,

To form a series of shear pulses required for receiving and outputting serial information in register 4, elements 93 and 72 are used.

To receive a signal. The address when rewriting information from register 4 to block 3 is AND 83.

Element 80 serves to receive a high level control signal when reading information from block 3 to register 4, as well as to receive the Reversal signal for block 3 using element 73.

Logical addition of signals The treatment for block 3 in all modes of operation of the device is carried out by element 87.

Element 97 is intended to receive clocks for register 4.

The control unit 1 operates as follows.

When the signal element 67 arrives at input 66 of the Initial Installation, the triggers 89 and 90 are set to the zero state. After that, the input 68 of the decoder 69 and the inputs 70, 71 and 74-elements 72, 73 and 75, respectively, begin to continuously receive the clock signals.

In the absence of a call to the device, the low-level signals are received at the inputs 88 and 91 of the decoder 75. Upon the arrival of the control signal at the input 84 and the corresponding binary code at the inputs 85 of the decoder 75, the latter issues a signal through the input 101 of the element 87. Accessing block 3. The period of the turn signals and, consequently, the recording period of the information of the input relay words in block 3 is determined by the repetition period control signals at the input 84 and the binary code at the inputs 85 of the decoder 75.

To read the information from block 3 into the UHC, the binary code of address a is fed to the inputs 77 of the decoder 78, so that a high level signal appears at one of the inputs 106 of the element 96. From the output of element 96, this signal is fed to output 46 of block 1, as well as to input 91 of the decoder 75, input 93 of the element AND 83, input 92 of the element AND 80, and also through input 94 of the element OR 95 to input 103 of the element AND 72. After that, a control signal is received from UCBM through input 23 of unit 1 to input 79 of element 80. This output 15 of unit 1 produces a single control signal that permits reading from block 3 and writing of a parallel code to register 4. This same signal arrives at the input 86 of element 73, from the output of which, as compared with the clock pulse, e About input 71, a signal is generated. Appeal to block 3 is transmitted via input 100 of element 87 to output 18 of block I. Simultaneously with the signal Appeal at output 62 of block 1, a clock signal is generated at input 99 of element 97, and a signal is generated in parallel ya record information from block 3 to the register

f

After that, the input signal 81 of the element 72 port the control signal from the UHEC, the duration of which determines the number of shift pulses at the output of the element 72.

In order to ensure the mode of diagnostic verification of register 4 by organizing its recording and reading, the UHCWD outputs to the inputs 77 of the decoder 78 an address code of. Three of this high level signal from the output I05 of the decoder 78 through the input 104 of the element 95 enters the input 103 of the element 72, which forms (with the help of the control signal of the SCWM at the input 70) a series of shift pulses coming through} the course 98 of the element 97 to the output 62 block 1.

In the diagnostics mode of the addresses of input words, block 1 works as follows. From UDCM to the inputs 76 of the decoder 69 receives the address code /. From the output 110, the decoder 69, the high level signal is fed to the input 112 of the flip-flop 90 and sets it in one state. From the moment when the trigger 90 is set to one, the Cyclic recording into block 3 of the information on the state of all outputs of the decoder 5 is made by the same signals. The same as when writing the information of input relay words In offline mode.

The operation of unit 1, when reading diagnostic information from unit 3, is similar to its operation, when it is read off-line.

In the mode of diagnostic checks unit 3 unit 1 operates as follows. Upon the arrival of the address code y to the input 76 of the decoder 69, the latter generates a high-level signal at the output 109, which, at the input to the input 11 of the flip-flop 89, sets it to one state. The signal from the output of the trigger 89 is fed to the output 44 of block 1 and to the input 88 of the decoder 75 and blocks the formation at its output of cyclic signals. Appeal to the block

3. From the output 44, the signal is fed to the input 47 of the multiplexer 33, connected to the information input 54 of the block 3, the output 58 of the register 4. After that, the input code 77 of the decoder 78 from the UDCM receives the address code a, which

leads to the appearance at the output of an element 72 of a series of shift pulses, which are used to record diagnostic information by a serial code in register 4. After the information is recorded in

the register 4 from the input 25 of block 1 to the input 82 of the element 83 from the UHEC receives a high-level control signal and, in the presence of a high level, a signal is generated at its input 93. A call to block 3, which

through the input 102 of the element 87 enters the output 18 of block 1 and ensures that the contents of register 4 are overwritten into the corresponding memory cell of block 3.

To write the diagnostic information to the next memory location of the UHAC unit 3, it modifies the address code A at the input 77 of the decoder 78, and the write cycle repeats.

Reading diagnostic information from unit 3 is performed in the same way as reading information from it offline.

The reset of diagnostic modes (flip-flop 89 and 90) is performed at the beginning

each cycle UCVM on the synchronization signal at the input 65 of the element 67.

UCVM also has the ability to forcibly reset triggers 89 and 90 at any time during the UCVM cycle, applying to input 76

decoder 69 address code q. In this case, a single high level signal from the output 108 of the decoder 69 enters through the input 107 of the element 67 to the inputs 113 and 114 of the flip-flops 89 and 90, after resetting which

The device resumes looping input relay words:

The counter 115 of the driver 2 is designed to receive at its outputs 125 and 126 binary codes used to form the addresses of the input relay words, as well as the cyclic control signals necessary for the operation of the device.

A trigger 117 serves to create a control signal defining the duration of the addresses of input relay words. Elements 118 and 116 are designed to form a reset signal for trigger 117.

Shaper 2 works as follows.

Upon arrival of the signal from input 35 to input 119 of counter 115 and input 120 of flip-flop 117, the latter are zeroed. After that, the input 121 of the counter 115, as well as through the element 118 to the input 122 of the element 116c of the input 37, the clock signals begin to flow continuously. Counter 115 begins counting the clock signals and, upon arrival of the signal at input 121, outputs an overflow signal from output 127, which, at input 128 of trigger 117, coaxes it.

After that, when cocking the j-ro bit (output 131) of the counter 115 at the input 130 of the element 116, a high level signal appears and the clock signal delayed by the element 118 at the input 122 of the element 116 enters the input 131 of the trigger 117. Thus, at output 39 driver 2 generates a control signal, the duration of which is determined by the moments of arrival of signals at inputs 128 and 129 of trigger 117, and its period is the period of overflow signals at output 127 of counter 115.

Binary codes n the lower bits of the counter 115 (output 126) are used to generate cyclic reversal signals of block 3, and binary codes of the higher bits (output 125) to form the address of the input relay words.

The synchronization of the counter 115 in the UDCM cycle is performed upon the arrival of the synchronization signal at its input 123, and the counter 115 records the binary code received at the inputs 124 from the shift block 63 in parallel.

In Figures 5 and 6, the timing diagrams of the input device exchange with the digital computer controller are detailed.

Claims (3)

1. A device for inputting information containing a control unit, a shift register, an address decoder, a group of amplifiers, a group of keys, n groups of separation elements and n groups of switches of received words, the input and output of the 1st group key () connected respectively to 1- The output of the address decoder and the first terminals of the switches of the received words of the 1st group, the second terminals of which are connected to the first terminals of the same dividing elements of the i-th group, the second terminals of which are connected to the input of the 1st amplifier of the group, the input synchronization, the input of the setup, the clock input, the address input, the first, second and third permitting inputs of the control unit are respectively with the same inputs of the device, the input of the shift register mode is connected to the first output of the control unit, and the output of the higher bit of the shift register is the information output of the device, which is characterized by the fact that, in order to expand the functionality by providing digital diagnostics of the device - body complexes and their increase 5, it contains two multiplexers, a buffer memory block, a cyclic address generator and a shift memory block, the output of which is connected to the cyclic information input 0 address driver, reset input, clock input, synchronization input, the first, second and third outputs of which are connected respectively to the initial setup input, the clock input and the synchronization input 5, the information input of the address decoder, the fourth enable input and the operation input of the control unit, the enable input of the address decoder is connected to the second output 0 cyclic address driver, the buffer access enable input of the buffer memory is connected to the second output of the control unit, the first, second and third information inputs, the first and second packages 5 and the main inputs and output of the first multiplexer are connected to the outputs of the group amplifiers, outputs of the address decoder, information output shift register, the third and fourth 0 by the outputs of the control unit and the information input of the buffer memory unit, the first and second information inputs, the control input and the output of the second multiplexer are connected respectively to 5 to the first output of the cyclic address maker, the address input of the device, the fifth output of the control unit and the address input of the buffer memory block whose recording input is connected to the first output The control unit 0, the information input, the clock input and the reset input of the shift register are connected respectively to the output of the buffer memory block, the sixth output of the control unit and the initial setup input of the device, and the low-order input of the shift register is the information input of the device. 2. Device pop. 1, characterized in that the control unit contains three decoders, two triggers, five elements OR and four elements AND, the first, second and third inputs and the output of the first element OR are connected respectively to the synchronization input and the input of the initial installation of the block, the first output of the first decoder and the reset inputs of both triggers, enabling input, information input, second and third outputs of the first the decoder is connected respectively to the clock input and the address input of the block, the installation inputs of the first and second triggers, the first and second inputs of the first element And are connected respectively to the clock input and the second pa the block decisive input, the first and second inputs and the output of the second element AND are connected respectively to the clock input of the block, the output of the third element AND and the first input of the second element OR, the second and third inputs and output of which are connected respectively to the outputs of the second decoder, the fourth element AND and the second the output of the block, the first and second inputs and the output of the third element OR are connected respectively to the output of the fourth element OR, the first output of the third decoder and the third input of the first element AND, the information input and The output of the third decoder is connected respectively to the address input of the block and the inputs of the fourth OR element, the output of which is connected to the fifth output of the block, the first and second inputs and the output of the fifth OR element are respectively connected to the outputs of the first and second And elements and the sixth output of the block, the first and the second inputs and output of the third element AND are connected respectively to the first enabling input of the block, the output of the fourth element OR, and the first output of the block, the first and second inputs of the fourth element And are connected respectively to the third enable input of the block and the output of the fourth OR element, the outputs of the first and second flip-flops are connected respectively to the third and fourth outputs of the block, and the information input and the first to fourth enable inputs the second decoder is connected respectively to the input of the operation, the clock input and the fourth block enable entry, the outputs of the first trigger and the fourth element OR. 3. The device according to claim 1, that is, so that the cyclic address driver contains a counter, an AND element, a trigger and a delay element, the input and output of which are connected respectively to the clock input of the driver and the first input And, the first and second reset inputs, the setup input and the trigger output are connected respectively to the reset input of the imager, the output of the And element, the overflow output of the counter and the second output of the imager, and the counting input, the recording input, the information input, the reset input, the high-order output , exit mla Shih bits and output j-ro discharge counter connected respectively to the clock input, input timing data input, a reset input, first and third the outputs of the driver and the second input element I. if s5 II ъ WffftfiM uhff t lC969l (Rig. G ftfcJ Rig. four 5 ZyVod information from the digital computer s p p p p p p p p p p p p p