SU1363227A2 - Device for interfacing sources and receivers with trunk line - Google Patents

Abstract

The invention relates to computing and can be used to interface a digital computer with measuring devices. The aim of the invention is to improve the speed of the device. The device contains a communication unit 1 with a trunk, a decryption unit 2, interrupt input 3, element OR 4, multiplexer 5, data register 6, address register 7, interrupt register 8, source data register 9, first group of 10 elements AND, dep.1if - the address torus 11, the second group 12 elements And, the receiver 13, the source 14, the trigger trigger 22, the source address decoder 23, the second pulse generator 24, the third driver 25 pulses, the generator 26 pulses, element 27, the element OR 28, the counter 29 addresses, memory block 30, readiness trigger 31, driver 32 imp write / read pulse, end decoder 33, first pulse generator 34. The device allows you to organize the exchange of information between the measuring devices and the main channel of the common, its use with increased speed. 1 il. (L with Oi 00 yu k

Description

The invention relates to computing and can be used to interface a digital computer with measuring devices.

The purpose of the invention is to increase the speed of the device.

The drawing shows a diagram of the interface device.

The device contains an interface unit 1 connection with the trunk, the unit 2 decoding control signals, input 3 interrupts unit 1, the element OR 4, multiplexer 5, register 6 receiver data, register 7 addresses, register 8 interrupts, register 9 data source, the first group 10 I elements, address decoder 11, second group I elements 12, receiver unit 13, source block 14, data bus 15 for transmission, bus 16 "Address data for reception, bus 17 for control, bus 18 for local communications, bus 19 synchronization, source data bus 20, receiver data bus 21, trigger 22 launch, descrambler

23 source addresses, second shaper

24 pulses, third pulse shaper 25, pulse generator 26, AND 27 element, OR 28 element, address counter 29, memory block 30, readiness trigger 31, write-read pulse shaper 32, write end decoder 33, first pulse shaper 34, addressable output 35 of the device, output 36 of the device clock and information output 37 of the device.

The device works as follows.

When the power is turned on, all elements of the device are reset, in block 2 a signal "rdy" is generated, which is fed through bus 18 to block 1.

The mode of operation of the device is determined by the primary address arriving at block 1 from the public main channel (not shown in the drawing). To access the selected receiver unit 13 in order to generate control and address signals to the external source device, when the primary address of the receiver arrives, unit 1 compares the incoming code with the device address, and if they match, the device is functionally connected to the public trunk channel and is configured to receive information from the public main channel. The next byte to the device is the secondary address, which specifies the address of the receiver unit 13, to which information is transmitted. In block 1, a signal "MSA" is generated, which, arriving at the first input of the register 7 of the address, records the address code of the block 13 of the receiver. When there is a zero in the "P resolution de-reg 7 address (PrA p) on the decoder 11, the received address code is decoded. In block 1, a "LACS" signal is generated, indicating that the device is ready to receive information. The incoming bytes of the instrumentation message are then entered into the receiver's data register, to which up to n bytes can be written (n is the number of bytes that the receiver 21 can pass in parallel). Each byte is entered into register 6 by the signals "Receive 1 byte," Receive 2 bytes, ..., "Receive n bytes, which are received

About along the bar 19, from block 2, in which they are formed by the signals "LACS" accompanying the reception of each byte. The "rdy" signal is reset by the "LACS" signal when each byte is received, and is again set to the "OASprd" signal. The reception of the last byte is accompanied by a signal coming from the public main channel. The signal "Receive p byte, in block 2, a signal is generated," Open receiver data keys,

0 which valve elements. And, and the n-byte word comes from the receiver's data register to the receiver's data bar 21. At the same time, a "Request" signal is generated by the "Receive n byte" signal in block 2

from which it arrives via bus 19 to elements AND of the second group, allowing the transmission of the signal "Request from the output of address decoder 11 to the selected receiver block 13 (rn is the number of receiver blocks and sources connected to buses 20 and 21).

Q At the request signal, the receiver block 13 enters an n-byte word from bus 21 and triggers trigger 22, allowing the formation of a signal. Receiver unit response in driver 24, in which signal is generated in receiver block 13

 “The answer then arrives in the form of“ O to the third input of unit 2, to the certificate of the end of data reception by the selected unit 13 of the receiver. In case of no signal "Answer in block 2, a signal is generated" Avariya, which from the third output of block 2 is written to the interrupt register 8, the n-byte word recorded in the receiver block 13, from its fourth output goes to decipher 23, the output of which is It is addressed by the output 35 of the device. At the output of the trigger 22, a signal "1" is set, which valves AND 27, allowing the clock pulses to exit the generator 26 pulses to the device output 36 and through the OR element 28 to the counting input of the address counter 29 and to the driver input 32. For each clock pulse launching an external source device (for example, an analog-digital converter), generating the cell address code of the memory block 30 at the output of the ad5 counter 29, as well as the write pulse at the output of the driver 32 when there is a signal “1 in its second m inlet. Synchronously with these signals from an external source device to

the information input of the memory block 30, which is the information input 37 of the device, enters an n-byte data word, which is entered into the selected cell of the memory block 30. As soon as in the memory block 30, the required data array is accumulated, determined by the number of sync pulses received at the address counter 29, the corresponding code from the output of the address counter 29 goes to the first input of the decoder 33, at the second input of which is set "1 from the trigger output 22 launch. The signal of the end of the recording from the output of the decoder 33 is supplied to the single input of the ready trigger 31. The ready signal from the output of the trigger 31 is fed to the fourth input of the source block 14, in which an interrupt signal is generated, which then enters from the first output of the block 14 to the interrupt register 8. When the flip-flop 31 is turned on, a reset pulse is generated in the shaper 34, which, arriving at the installation inputs to the zero state of flip-flop 22, flip-flop 31 and address counter 29, resets them, completing the data recording cycle from the external source device to the memory block 30.

The operation of the device in the mode of data transmission from the source unit 14 to the public channel is specified by the primary source address (MTA), which, coming from the public channel to unit 1, connects the device to the public channel and configures it to transmit information. The secondary address of the MSA then arrives, similarly to the mode of receiving information, to access the selected source block 14. The "Request T" signal arrives at the selected source unit 14, from the fourth output of which, through the OR element 28, it arrives at the counting input of the address counter 29 and the first input of the driver 32. The output cell of the memory block 30 is generated at the output of the address counter 29, the output of the imaging unit 32 is a read enable signal. At the output of memory block 30, a n-byte data word is set, which is fed to the third input of source block 14. At the same time, the signal "Request t in the imaging unit 25" generates a signal "Response of the source block to the input of unit 14 of the source. By this signal, a n-byte data word is set up on the source data bus 20 and a "Response" signal is generated, which is sent to block 2, in which the "Enter word is then received signal on bus 19 to the source data register 9, permitting parallel input to it n-byte data words from block 14 source. According to the signals "Transmit 1 byte," Transmit 2 bytes, ..., "Transmit n

0

the byte formed in block 2, the word written in register 9 is rewritten byte-byte through multiplexer 5 to block 1 and further to the public main channel. The transfer of the last byte of the data word is accompanied by the signal “EO1prd formed in block 2. To transfer the entire data array recorded in memory block 30, it is necessary to repeat similar data transfer operations as many times as the memory block of memory block 30 takes the recorded data array.

The initiation of a call to the source unit 14 may be effected by an interrupt signal generated at the end of a cycle of recording data from the external source device to the memory unit 30.

Claims (1)

Invention Formula 0 five five A device for interfacing sources and receivers with a trunk via aut. St. No. 1252788, characterized in that, in order to improve the speed of the device, a trigger trigger, a source address decoder, three pulse generators, a pulse generator, an AND element, an OR element, an address counter, a memory block, a readiness trigger, an end-of-write decoder are entered into it. , write-read pulse driver, single trigger trigger input is device input 0 to connect to the receiver start output, the start trigger zero input is connected to the output of the first pulse shaper, the readiness trigger zero input and the address counter reset input, the start trigger output is connected to the input 5 of the second pulse driver, the first input of the AND element and the gates of the write-read pulse generator and the write end decoder, the second input of the AND element is connected to the output of the pulse generator, the output of the AND element is connected to the first input of the OR element and is the output of the device to the input source address synchronization input, the second input of the OR element is connected to the input of the third pulse generator and is the device input for connecting to the output of the source request, the output of the OR element is connected to The address input of the address counter and the start input of the write-read pulse generator, the output of which is connected to the write-read input of the memory block, whose address input and information end of the write end decoder are connected to the output of the address counter, the information input of the memory block the input of the device for connecting to the information output of the source, the output of the memory block is the output of the device for connecting to the information input of the source, the outputs of the third and second pulse shapers are 0 five 5 13632276 with the outputs of the device for connection to connect to the ready input, respectively, to the inputs of the source confirmation, the input address address decoder input and the receiver, the output of the decoder is the input device for the recording sub-end connected to the unit input to the output of the receiver , the output of the ready trigger, whose output of the source address decoder's gateway is connected to the input of the first driver, the output of the device for connecting pulses, and is the output of the device to the address input of the source Chnik.