SU1302289A1 - Interface for linking electronic computer with using equipment - Google Patents

Abstract

The invention relates to computing technology, in particular, to input devices of information in a computer, and may find application in organizing the exchange of information between computers in many 22 processor computing systems and local computer networks with an arbitrary configuration. The aim of the invention is to increase speed. The device contains a control decoder 1, a response trigger 2, a maintenance switch 4, an input switch 6, a request switch 3, a clock generator 8, a resolution decoder 5, a first word load trigger 1 7, an array length counter 15, a RAM block 13, a trigger 18 session endings, address multiplexer 16, address counter 14, control trigger 9, channel counter 7, four AND elements 10,11, 20.21, NOT element 12, delay element 19. 3 il. c (L 27 (PU8./

Description

The invention relates to computer technology, in particular, to devices for inputting information into electronic computers, and can be used in organizing the exchange of information between computers in multiprocessor computer systems and local computer networks with an arbitrary configuration.

Figure 1 shows the block diagram of the device; figure 2 - timing charts of receiving an array of information; on fig.Z - algorithm of the computer in the case of receiving an array when using this device.

The device contains control decoder 1, response trigger 2, request switch 3, tracking switch 4, resolution decoder 5, input switch 6, channel counter 7, clock generator 8, control trigger 9, second 10 and first 11 elements AND, element 12, memory block-13, count-Chick 14 addresses, array length counter 15, address multiplexer 16, first word loading trigger 17, session end trigger 18, delay element 19, third 20, fourth 21 And elements, first input 22 , the second output 23 of the device, the third input 24, the third you od 25, second input 26, a group of outputs 27, a first group of inputs 28, a second group of inputs 29, the third group 30 of inputs and a first output 31.

In Fig. 2, the following symbols are accepted: A-A. Diagram at the output of control trigger 9; B - diagram on the unit output of the trigger 17 load the first word; B - diagram on; the output of the maintenance switch 4; G - diagram at the output of the third element And 20; D is the diagram at the output of the delay element 19; E - diagram at the output of the trigger 2 response; W is the diagram at the output of the second element And 10; And - the diagram at the output of the fourth element And 21; K - diagram at the transfer output of the counter 15 of the array length; L is a diagram at the exit of the session 18 trigger 18; M - diagram at the third output of the decoder 1 control.

The decoder 1 control is designed to form on its outputs control signals, providing a change in the state of the elements

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the memory of this device in accordance with the control information, post; from its own E.VM through the control panel 1st input 26 of the device. The first output of the control decoder 1 is connected to the asynchronous zero input of the trigger 2 response and to the asynchronous zero input to the first word loading trigger 17 and is intended to set these triggers to the zero state. The second output of the decoder 1 provides the formation of the recording control signal -to the counter 7 channels of information, which then appears at its output, and is connected to the control input of the counter 7 channels. The third output of the decoder 1 control is connected to zero; the control trigger input 9 and the zero entry of the session end trigger 18 are designed to set the triggers 9 and 19, 5 to the zero state after the computer has finished reading the received information input device.

The trigger 2 response is intended to form at the output a response signal indicating the receipt of the next word of information from the transmitter device. The output of the trigger 2 response must be connected to all subscribers, namely, one of their input acknowledgment. UNA Trigger Input 2 Response is the asynchronous trigger setup input; ra 2 in a single state. Synchronous zero input of trigger 2 is intended to be set to zero const. naye on the leading edge of a pulse arriving at this input. The asynchronous zero input of trigger 2 serves to8 reset it to the zero state when a corresponding signal appears on it.

The request switch 3 provides for the selection of one of the request signals for establishing a communication session, received at one of the jero external inputs, in accordance with. control information at its control input.

The maintenance switch 4 is designed to select one of the attendance inputs 30 connected to the subscriber with whom a session is established and from which information is received.

One of the inputs 30 is selected by the switch.

4 according to the binary code on its control input. The control signal input received through the switch 4 selected by the switch indicates that a new information word has been installed on the corresponding group of inputs of the input switch 6.

The resolution decoder 5 is designed to form on one of the inputs, which are a confirmation output 27, a signal confirming the establishment of a communication session with one of the subscribers in accordance with the information on the control input and in the presence of a permission signal on the enabling input. Decoder Outputs

5 resolutions are connected with respective subscribers.

The input switch 6 provides the choice of one of the groups of inputs that form the second group of inputs 29 of the device, and the transfer of information from it to the group of outputs in accordance with the information on the control input.

Channel counter 7 is designed to detect a request arriving at the device request input 28, as well as fixing the channel code for which the request is detected and controlling the resolution decoder 5, the input switch 6 and the maintenance switch 4 according to this code. Counter 7 provides the increment code at its output when it arrives at the counting input signal from the output element And 11.

The trigger 9 control is designed to memorize the fact of establishing a communication session.

The RAM unit 13 is intended for buffering an array of information coming from the output of the input switch 6. The information is recorded in the RAM block 13 under the influence of its corresponding input of the write control signal. At the rest of the time, the RAM block 13 is switched on to read in accordance with the addresses supplied to its address input,

The address counter 14 is intended for the generation of addresses by which information is recorded in the memory unit 13. The information inputs of the counter 14 are connected to O, which allows; load Constant O into counter 14 under the action of a load signal sent to its load input input from the output of the switch 3 requests. The increment of the contents of the striker 14 occurs under the leading edge of the signal arriving at its countable input from the output of the elements And 10,

The array length counter 15 is designed to count the number of words contained in the buffered array of information. The first word of the array containing information about its length is loaded into counter 15, and it is processed in subtraction mode.

Before operation, the device is reset by a computer signal. In this case, the control decoder 1 generates signals at its first and third outputs 9 thereby becoming zero states: a 2-response trigger, a control trigger 9, and a session termination trigger 18. When a session is established, a single request signal appears at the input 28 of the request.

When the next sync pulse from the generator 8 arrives, the channel counter 7 increments the binary code at its output, thereby connecting 3 requests to one of the input line 28 request groups to the switch output. When forming at the output of the counter 7 channels of the code corresponding to the number of the input on which there is a request, a single signal appears at the output of the switch 3 of the requests. It is fed through the element NOT 12 in inverse form to the first input of the element 11 and prohibits the supply of clock pulses to the counting input of the counter of 7 channels. In addition, the signal from the output of the switch 3 requests goes to the single input of the control trigger 9 and to the input of the record of the address counter 14. In this case, the control trigger 9 is set to one, and zero is loaded into the address counter 14a (diagram A, FIG. 2), and the transition to the one state trigger 9 causes the loading of the first word to the unit one (diagram B, FIG. 2) A zero signal is set at the zero output of the trigger 9, blocking the change in the input state of the 7-channel counter, thereby making it possible to receive information from the source device that sent the request

per session. A single signal from a single output of the trigger 9 permits the confirmation of the decoder 5 and opens the element 10 for passing the tracking signals from the output of the tracking 4 switch. The number 7 recorded at the output of the counter corresponds to the channel number over which information should be received. The code of the channels from the output of the counter 7 enters the tracking switch 4 and the input switch 6, providing connection to their outputs of the required tracking input 30 and information input 29 bus. The resolution decoder 5 decodes the channel code to one of the output lines 27 confirming. A single signal confirming to the source device the fact of establishing a communication session. After this, direct reception of information by this device begins.

The first word of the transmitted array contains information about the length of the array. When the switch 4 detects a tracking signal at input 30 of a single signal (diagram B, Fig. 2), it is transmitted to output of an element 10. This signal arrives as a recording signal to the operational memory unit 13 and through an element 20 controlled by a signal from the single output of the trigger 17 of loading the first word, is fed to the input of the record of the array length counter 15 (diagram G, FIG. 2). In this case, the first input word is already set at the input 29 of the device. On the leading edge of the tracking signal, the first word is immediately loaded from the output of the input switch 6 into the RAM block 13 and into the array length counter 15, and the response trigger 2 is set to 1. The response signal from the trigger output 2 goes to the subscriber. At the same time, the follow-up signal from the output of the AND 10 element is fed to the delay element 19 (diagram D, Fig. 2), the response time of which corresponds to the time T required to record information in block 13. RAM and in the counter 15 array length. After time T at the output of delay elements 19, a signal arrives at the synchronous zero input of trigger 2 response.

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The latter is reset to O (diagram E, Fig. 2). Removing the dial tone allows the source device to clear the tracking signal. The falling edge of the tracking signal from the output of the AND 10 element is applied to the counting input of the address counter 14 (diagram G, Fig. 2) and to the synchronous zero input of the first word loading trigger 17. At the same time, the contents of counter 14 are incremented by one and through the address multiplexer 16, controlled by a signal from the unit arm of the session end trigger 18, are sent to the address input of the RAM 13 as the next address, and the first word load trigger 17 is set to zero the At the second input of the AND element 20, a zero signal appears from the output of the trigger 17, and a single signal appears at the second input of the AND 21 element.

When issuing the second and subsequent words, together with the tracking signals, the signals from the output of the element And 10 are fed to the recording input of the RAM block 13, through the element 21 and it subtracts the input of the array 15 counter (the diagram of FIG. 2) and the counting input counter 14 addresses. On the leading edge of these signals, each new word of the array arriving at the information input of block 13 from the output of the input switch 6 is written into the block 13, and the array length of the counter 15 decreases with each subsequent load. On the falling edge of these signals, an increase in the content of the counter of address 14 occurs, which serves as the address for recording the next word of the array in the operational memory 13. After the last word in the array is transmitted, the subscriber removes the request at his output of requests, and a zero signal appears at the output of the switch 3 requests of the device-receiver.

When the device receives the last word of the transmitted array, the array length counter 15 is zeroed out and outputs a signal to its transfer input (chart K, Fig. 2). This signal is fed to the single input of the session termination trigger I8 and sets it to the single state

(diagram L, figure 2). In this case, a signal appears at the output of the device interrupting the computer that the input device receives the array, and the address multiplexer 16 connects its first information input to the address input of the RAM block 13. In this input, the computer reads the addresses through the device address input 24, receiving the information read out from the memory block 13 at the information output 23 of the device. Upon completion of reading the array, the computer sends a signal to the control input of the device, after the decoder command 1 control generates a signal at its third output (diagram M, FIG. 2). The control trigger 9 and the session end trigger 18 are set to O, whereby the counter 7 is unlocked, the code at its output is changed, and the confirmation signal is removed from the corresponding output of the resolution decoder 5, indicating that the subscribers are disconnected.

Claims (1)

Formula invented about te A device for interfacing a computer with subscribers, comprising a control decoder, a response trigger, a maintenance switch, an input switch, a request switch, a clock generator, a resolution decoder, a control trigger, a channel counter, two AND elements, a NOT element, and the channel counter information input is the input of the device for connecting to the information output of the computer, the information input of the control decoder is the input of the device for connecting to the control output of the computer, the group of outputs of the decoder p The solution forms a group of outputs of the device for connection. to the subscriber confirmation inputs, the group of information inputs of the request switch forms a group of device inputs for connecting to the subscribers request outputs, the group of information inputs of the input switch forms a group of device inputs for connecting to the subscribers information outputs, the group of information inputs of the tracking switch forms a group of inputs devices for connection to sync 5 fO 5 20 25 - thirty the subscriber inputs, the response trigger output is the output of the device for connecting to the subscriber sync inputs, the output of the request switch is connected to the single control trigger input and the input of the HE element, the output of which is connected to the first input of the nepBoi o I element, the output of which is connected to the counting input the channel counter, the output of which is connected to the information input of the resolution decoder, with the control inputs of the request switch, the input switch and the maintenance switch, the output of the maintenance switch with It is connected to the first input of the second element I, the second input of which is connected to the authorizing input of the resolution decoder and the unit output of the control trigger, the zero output of which is connected to the second input of the first element I, the third input of which is connected to the output of the clock generator, the first The second and third outputs of the control decoder are connected to the first zero input of the response trigger, the write input of the channel counter, the zero input of the control trigger, respectively, are distinguished by the fact that, in order to increase the speed ystvi, it entered the address counter, the address multiplexer unit operative array length counter, load trigger of the first word, two I elements, delay element, the information output of the RAM block is the output of the device for connecting to the computer information input, the first information input of the address multiplexer is the device input for connecting to the computer address output exit trigger exit session is connected to the control input of the address multiplexer and is the output of the device for connecting to the interrupt input of the computer, while the second zero input of the response trigger is connected to the output of the delay element, the input of which is connected to the input of the record of the operating memory block, the counting input of the address counter, the first inputs of the third and fourth elements, And, the first zero input of the trigger of loading the first word, the output of the second element I, the single input of the response trigger, the first zero input of which is connected to the second zero input of the loading trigger of the first word, the unit and zero outputs of which are connected to the second inputs of the third and fourth elements And, respectively, whose outputs connected to the recording input and the counting input of the array length counter, respectively, the information input of which is connected to the output of the input switch and to the information input of the block operatively th memory whose address input is connected to the multiplex output copy of the address, the second information input of which is connected to the output of the address counter, the recording entry of which is connected to the output of the request switch, the transfer output of the array length counter is connected to the single input of the session end trigger, the zero input of which is connected to the third output of the control decoder, the word is connected to a single control trigger output. fU2.2 C Start J Reading d computer d / JOHbi array fnep6oe slobo) Reading is weak 6 computers 1rin then there is no last slobo Yes (Horses, J Fig.Z Compiled by S. Pestmal Editor I.Nikolaychuk Tehred L.Oleinik 1217/48 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader A.Ilyin