SU1647580A1 - Device for interfacing a computer with a data transmission channel - Google Patents

Abstract

The invention relates to the field of computing and can be used in distributed computing systems, such as tele-automatic queuing systems. The purpose of the invention is to increase the speed and increase the reliability of information exchange. The device contains a shift register, a synchronization node, a pulse generator, memory blocks, counters, a shaper of control signals, an input and output link signal amplifiers, a serial code-to-parallel conversion node, input control and mode setting nodes, a decoder of the beginning and end messages, memory control node, output switch, output amplifier block. Зз.п, ф-лы, 10 Il.

Description

The invention relates to the field of computer technology, in particular to devices for interfacing a computer with a serial data transmission channel, and can be used in distributed computing systems, for example, in tele-automatic queuing systems.

The aim of the invention is to increase the speed and reliability of the exchange of information.

FIG. 1.2 shows the block diagram of the proposed device; in fig. 3-8 are functional diagrams of a synchronization node, a control signal generator, an input control node, an encoder of the beginning and end of a message, a mode setting node, a reception control node; in fig. 9.10 - timing diagrams of the proposed device.

The device contains (Fig. 1, 2) transmitting 1 and receiving 2 channels of the device,

shift register 3, synchronization node 4, pulse generator 5, first memory block 6, second memory block 7, first counter 8. driver of control signals 9, output amplifier 10 of a communication line, input amplifier 11 of a communication line zi, a serial-to-parallel conversion node 12, an input control node 13, a decoder of the beginning and end of the message, a mode setting node 15, a reception control node 16, second and third counters 17, 18, third and fourth memory blocks 19, 20, switch 21 output signals, block 22 output amplifiers A computer, a computer information output group 23, a message termination bus 24, a computer control output group 25 transmitting 26 and a receiving communication part 27, a computer information input group 28. group 29 of the control inputs of the computer, the positions 30-35 denote the inputs and outputs of the synchronization node 4,

ABOUT

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positions 36, 37 - outputs of the generator 5 pulses, positions 38-41 denote the inputs and outputs of blocks 6, 7 of the memory, positions 42-45 denote the inputs and outputs of the serial-to-parallel conversion node 12, position 46 denotes the output permit of the node The 13 input controls, 47-48 positions denote the outputs of the decoder 14, the start and end of the message, 49-52 positions the inputs and outputs of the mode switching nodes 15, 53-57 denote the outputs of the receiving control unit 16, 58, 59 the outputs of the counters 17, 18, positions 60-68 marked g a group of information outputs of blocks 19, 20 of memory, node 4 of synchronization (Fig. 3} includes elements AND 69-70, triggers 77-74, element AND-OR 75. Position 76 denotes the input of the control signal generator 9 ( Fig. 4). The driver 9 of the control signals contains the element AND-OR 77, the triggers 78-79, the elements OR 80-81.

The input control unit 13 (Fig. 5) contains the triggers 82, 83, elements M 84 and I-NE 85. 8, the decoder 14 of the beginning and end of the message (F ig 6) includes decoders 86-88, counter 89, elements VI90, 91, triggers 92-95. Positions 96-102 denote the inputs and outputs of the node 15 (Fig. 7). The setting mode unit 15 comprises a delay element 103, a trigger 104, elements AND 105-106, elements OR 107-108.

Positions 109-116 designate the inputs and outputs of the reception control unit 16 (Fig. 8). The node 16 includes the triggers 117-122, the elements of AND-ILY J23-126, the elements VI 127-131, the element AND LI 132.

The transmitting channel 1 converts the binary code received from the computer and the serial code transmitted over the communication line. Receiving channel 2 provides conversion of serial binary code from a communication line to a parallel one, which goes to the computer. Register 3 shift provides storage of computer words and convert it to a serial code. The synchronization node 4 provides synchronization of the operation of the nodes of channel 1. The pulse generator 5 generates a set of clock frequencies necessary for the operation of the device.

. Blocks 6 and 7 of memory provide storage of computer messages. Counter 8 generates control signals at the address inputs of memory blocks 6, 7. The control signal generator 9 receives control signals from the computer and generates control signals for the computer. The 10.11 line link attenuators match the input and output signals of the communication line with the permissible levels of operation of the elements of the device. Serial conversion node 12

code in parallel can be implemented, for example, on a KR581 8A1 microcircuit. The input control unit 13 generates control signals for the node 12, 16 and the decoder 14. The decoder 14 starts and

0 of the end of the message provides decryption of the message header and the symbols defining the end of the message. Nodes 15 and 16 control the writing and reading of information from blocks 19 and 20. Counters 17 and 18 serve

5, to determine the length of the input messages, form signals from the address inputs of the memory blocks 19 and 20. Blocks 19 and 20 of memory are used for intermediate storage of messages from the communication line. Switch

0 21 output signals provide information to the information inputs of a computer from the outputs of one of the meters 17 and 18, and Block 22 of the output amplifiers are used to match the output circuits of the memory block 19 and 20 with the input circuits of the computer. The device works in two modes:

1. The transmission mode in the communication line.

2. The reception mode of the communication line.

In the transmission mode, the data received from a computer in a parallel binary code is converted into the communication line by channel 1 of the device into a serial binary code. The message from the computer is initially recorded in the memory block 6, and then transferred to the communication line, the computer programmatically controls the process of recording information in the buffer memory, analyzing the ready signal from the device.

The information word from the computer (group 0 23 outputs) is entered into the shift register

3. With output 38 of which in a sequential code is fed to the input of memory block 6. The message from the computer is entered in the memory block 6, and then through the amplifier 10 is transmitted to

5 transmission line portion 26. The computer controls the process of transmitting information by signals on a group of 25 outputs. Node 4 synchronizes the operation of the register 3 shift, blocks of 6.7 memory counter

O 8 and driver 9 control signals.

After entering the block 6 of the memory of each information word from the computer at the output 33 of the counter 8, a signal appears

5 unit level, which establishes the internal circuits of the node 4 for receiving the next word from the computer. During the recording of the message from the computer to the memory unit 6, the signal on the bus 24 from the computer has a low level. Therefore, when outputting a message from a computer to a block

7 memory sticks zeros. After the entire message has been output, the computer transfers the signal over the bus 24 to a single state. In the next cell of the memory block 7, at the same time, enter the unit, which, when reading information from the memory, will serve as a sign of the end of the message.

The computer then nulls the counter 8 of the signal to the bus group 25 and proceeds to reading the information from blocks 6 and 7 of the memory. The control signals of the output group 31 of node 4 translate into a read mode blocks b and 7 of memory. The frequency of the read pulses that go to the input of the 6 m 7 memory blocks and, consequently, the frequency of the signals in the communication line are determined by the frequency of the generator 5.

Reading information from memory blocks b and 7 is carried out until a single signal appears at the output 41 of memory block 7, which is fed to the input of the control signal generator 9. From the output of the imaging unit 9, computer readout 29 receives a ready signal, which serves for the computer as a sign that the message has been transmitted to the transmitting part 26 of the communication line. Control signals for a group of 25 computer outputs reset the internal circuits of the transmitting part of the device,

The procedure / rz of transmitting the message ends there.

In the receive mode, an intermediate accumulation of messages coming from the communication line into the device memory and the subsequent input of these messages into the computer are used. A message arriving from the communication line is recorded in one of the blocks 19 or 20 of the memory. Selecting a specific memory block for recording messages from the device memory into the computer in it, for example, if a new message arrives from reading the information from memory block 19, then it is recorded in memory block 20.

Thus, the device allows simultaneous recording of a message from the communication line e of one of the buffer memory blocks and reading information in the computer from the second memory block of the receiving part of the device.

Information from the outputs of the switch 21 and the block 22 of the output amplifiers is supplied to a group of 28 information inputs of a computer simultaneously on different information buses. Therefore, the computer has the ability to read the length of the message received by the device from the communication line and the data contained in the message. The state of the outputs of the counter 17 corresponds to the address of the selected memory cell block

19, and the exit state of the counter 18 corresponds to the address of the selected cell of memory block 20

After the group of characters corresponding to the beginning of the message arrives from the communication line, a single level signal appears at the output 47 of the decoder 14. Node 16 selects one of the memory blocks, for example a block; 19, the length of the message being written to it, After a unit level signal 15 is outputted at the output 47 of the node 15, and if the memory block 19 is selected for recording, the logical 1 signal appears at the output 51 of the node 15 and the counter

5 17. The synchronization of the counter 17 from the output 54 of the node 16 receives counting pulses, which successively change its state in accordance with the number of received message symbols.

After arriving from the receiving part 27 of the communication line of a group of symbols corresponding to the end of the message, the output 48 of the decoder 14 generates a signal

5 is a single level on which a ready signal is generated on one of the buses of group 29 of outputs. It serves as a sign for a computer to have a message in the device buffer memory. The computer reads the state

0 of the counter 17, corresponding to the length of the incoming message from the communication line, from the output of the switch 21. Then the computer exposes a combination of control signals on the bus group 25. which enters the group

5 inputs of the node 16, changes the state of the output group 50 of the node 16, which causes the counter 17 to reset by a signal from the output 51 of the node 15. After that, the computer sets a new combination of control signals at the output 25

0 for node 16. With a signal from output 55 of node 16, memory block 19 is put into read mode.

Periodically in the process of inputting a message to the computer, node 16 generates a signal

5 readiness for a group of 29 tires by which the computer reads the next message word from the buffer memory.

The computer analyzes each received message word. When detecting characters

At the end of the computer message, the combination of control signals is set to group 25 of the output of the driver. The initial state of the circuit 16 of the node 16 is reset.

This completes the entry of the message in the computer.

Node 4 synchronization (Fig. 3) works as follows. Element AND 69, triggers 71. 72, AND-OR 75 element are involved in the memory recording mode. The computer sets the Selected signals and Output on the outputs.

61, 62 The Bus 1 signal at output 63 is at a low level at this time. The signal from the output of the element And 69 triggers 71 is set to G, and the signal from the output 65 of the node A enters the parallel code from the computer in the 3-shift register. Trigger 72 is set to one at the sync input.

The pulse sequence of pulses goes from output 37 to input of node 4, trigger 72 is cocked and through element I-SLI 75 enters control input of shift register 3, and from output 32 to counter input 8. After the machine word is written into the memory of synchronization input trigger 71 is reset.

8, the reading mode from the memory and the output of information to the communication line are elements AND 70, triggers 73, 74, and AND OR 75 element. In this mode, the output 63 signal is low. When a single level appears at the outputs 61.62, at the output of the element And 70 a level of Logic 1 appears, which cocks the trigger 73. The clock signal arriving at the synchronization input of the trigger 74 coaxes it, allowing the formation of clock pulses at the output of the element M -OR 75. The pulse sequence at the output of the AND-OR element 75 determines the pulse frequency in the communication line. Shaper 9 control signals generates Ready 1 and End Operation. The Ready signal G appears at the input of the computer in two cases: after each machine word is recorded in the device memory block 6 and after a message is issued from the memory to the communication line, and accompanied by a Completed signal. In the first case, a ready signal is generated by an AND-OR 75 element, a trigger 78, an OR 80 element. In the second case, a ready signal is generated by a trigger 79 and an OR 80 element.

The input control unit 13 (Fig. 5) provides for the generation of a control signal for the serial to parallel code conversion unit 12. Reception of each character from the communication line is accompanied by a reception gate arriving at input 44 of node 13. When a clock signal appears at output 37, trigger 82 is charged. A single signal level from an output of an element 84 translates into a single state a trigger 83, from which the AND-NE element 85 generates a control signal at the output 45. At the output 46 of the node 13, a permitting signal is generated for the decoder 14 and the node 16.

The decoder 14 of the beginning and end of the message analyzes the incoming message and, when characters appear corresponding to the beginning or end of the message, generates a single level signal at output 48 or 47. In FIG. Figure 6 shows the decoder scheme for the case if, for example, the symbols of the ECDC of the Russian alphabet serve as a sign of the beginning of the message, and if the end sign is an IUUH symbols. If the character code 3 arrives at the input 43 of the decoder, then the trigger 92 is cocked, when the next character C appears at the input of the decoder, the trigger 93 is cocked and then

5, when new symbols 3 and C are received, triggers 94 and 95 are successively cocked. The unit level at the output of trigger 95 corresponds to the sign of the beginning of the message and is fed to the input 47 of the installation node 15

0 mode.

If the code of any other character appears at the input of the decoder 14, then the triggers 92-95 are reset by the signal from the output of the element AND 90, When the characters H

5 at the input of the counter 89 sequentially changes its state. After the arrival of the fourth character H, the output 48 of the decoder 14 produces a single-level signal corresponding to the sign of the end of the general. If the code at the input 43 of the decoder does not correspond to the code of the symbol H, then the counter 89 is reset by the signal on the output 46 through the element AND 91.

Consider in more detail the procedure

5 receiving messages After the group of characters corresponding to the beginning of the message arrives from the communication line, output 47 from the mode setting node 15 receives a pulse signal that sets the trigger 104,

0 if there was a logical 1 signal at its information input, this state of the trigger corresponds to the selection of memory block 19 Pulse signal from the output of the delay element 103 through elements 105

5 and OR 107 enters from the output 51 of the node 16 to the input of the installation of the counter 17, has folded it. The signal from the output of the element And 105 of the node 15 is fed to the input 99 of the node 16 and sets the trigger 117. In this case, the memory block 19

0 is transferred to the read mode by control signals from the outputs 111 and 112 of the node 16 (Fig. 8). The pulse sequence coming from the output 46 to the node 16, through the AND-OR 125 element enters the synchronization input of the synchronization counter 17, the state of which corresponds to the selected memory cell of the block 19. When the characters corresponding to the end of the message arrive from the communication line, 48 at node 16 there is a unit level that sets

the counter 18 and puts the memory block 20 in the read mode. From the trigger output 119, the Ready signal 2 arrives through the OR element 132 at the computer input 116, informing the computer that a message is stored in the memory / device. The computer receives a message length corresponding to the state of counter 17, and generates a unit level signal at input 110 of node 16. According to this signal through element AND 129 of node 16 and element OR 107 of node 15, counter 17 is triggered. A signal from input 110 of node 16 sets a trigger 121 , allowing the formation of a pulse sequence of read control signals from the memory at the output of the AND-OR element 125. The computer gates the reception of data by pulse signals from the output 133 (Fig. 8).

After the computer message has been entered, a single-level signal appears at input 109 of node 16. This signal from the output of the AND-OR element 123 resets the trigger 119, which results in the removal of the Ready 2 signal from the output 116 at the computer input. completed

If a new message arrives at the time of reading the message from the memory block 20, then the information input 96 of the trigger 104 of node 15 will be a logical 0 signal from the output of the trigger 119 of node 16. A pulse signal from the output 47 at node 15 clears the trigger 104. A trigger 118 of node 16 is set to one state at input 100 through element 106 of node 15. At outputs 113, 114 of node 16, the recording control signals of memory block 20 are generated. In this way, simultaneous recording of a message from a communication line to memory block 20 and reading of information in a computer from memory block 19 are performed.

The Error signal is generated at the output 115 of the element And 131, if both memory blocks contain messages (triggers 119 and 120 of node 16), and the computer does not receive any of the messages (triggers 121 and 122 are reset).

Claims (4)

1. A device for interfacing a computer with a data transmission channel, containing input and output amplifiers of communication line signals, a first counter, a shift register, a group of information inputs of which is a group of information inputs of a device for connecting to a computer, a synchronization node, a driver of control signals pulse generator and switch output signals, and the input of the input signal amplifier communication lines and the output of the output signal amplifier of the communication line are the corresponding input and output of the device for connection to the information output and the input of the data transmission channel, the group of mode inputs of the synchronization node is a group of inputs of the device for connection to the group of clock outputs of the computer, and the clock input is connected to 0 the first output of the pulse generator, the first group of outputs of the control signal generator and the group of outputs of the output switch are the corresponding groups of outputs of the device for connection to the groups of synchronizing and information inputs of the computer, in order to increase the speed and reliability of the exchange information entered into the device with 0 of the first through fourth blocks of memory, two counters, a serial code-to-parallel conversion node, a decoder for the start and end of a message, a mode setting node, an input control node, a receive control node and an output amplifier block, the first group of outputs of the synchronization node being connected to the group synchronization inputs of the shift register, the output connected to the information 0 by the input of the first memory block, the output of which is connected to the input of the output signal amplifier of the communication line, the group of outputs of the first counter is connected to the groups of address inputs of the first and second blocks 5 memories, groups of control inputs of which are connected to the second group of outputs of the synchronization node, the first output and the first synchronization input of which are connected respectively to the counting input and 0 by the transfer output of the first counter, and the second output and the second synchronization input, respectively, with the first input of the condition and the first output of the driver of the control signals, the first and second 5, the synchronization inputs and the second input of the condition of which are connected respectively to the transfer output of the first counter, the first output of the pulse generator and the output of the second memory block, information 0 whose input is the device input for connecting to the output of the sign of the end of the computer output, a group of clock inputs of the control signal generator is connected to a group of device inputs 5 for connecting the synchronization outputs of the computer and the group of synchronization inputs of the receiving control node, the first group of outputs of which is connected to the group of outputs of the device for connecting to the group of synchronizing outputs of the computer, and the second and third groups of outputs respectively to the groups of control inputs of the third and fourth blocks of memory, the groups of outputs of which are connected through the block of output amplifiers to the group of outputs of the device for connecting to the group of information inputs of a computer, the reset inputs of the second and third counters are connected respectively to the first and the second outputs of the mode setting node, the group of state inputs and the output group of which are connected respectively to the fourth group of outputs and the group of inputs of the mode of the receiving control node, sync input and first to third outputs connected respectively to the first output of the decoder of the beginning and end of the message, the control input of the output switch and the counting inputs of the second and third counters, the output groups of which are connected respectively to the first and second groups of information inputs of the output message switch and address groups the inputs of the third and fourth memory blocks, the groups of information inputs of which are connected to the output group of the serial to parallel conversion node and the group of information inputs of the decoder of the beginning and end of messages, the second output of which is connected to the sync input of the mode setting node, and the enabling and sync inputs are respectively with the first output of the input and readiness control node of the serial to parallel conversion node, enabling input, readiness output , the clock and information inputs of which are connected respectively to the second output and the clock input of the input control unit, the second output of the pulse generator and the output of the input signal amplifier of the communication line, the clock input and the first output of the node at the input control are connected respectively to the second output of the pulse generator and the enable input of the receiving control node. 2. The device according to claim 1, characterized in that the input control node contains two triggers, an AND element and an NAND element, the information input of the first trigger being the synchronization input of the node and connected to the reset input of the second trigger, the inverse output of the connected to the reset input of the first trigger, the synchronization input of which is the clock input of the node and connected to the first inputs of the AND AND AND-NOT elements, the second inputs connected respectively to the forward, outputs the first and second triggers, the outputs of the elements AND-NOT and AND are connected respectively to the second output of the node and the synchronous input of the second trigger, the information input of which is connected to the direct output of the first trigger and the first output of the node. 3. A device pop 1, characterized in that the reception control node contains six triggers, four AND0 elements, AND five elements and an OR element, the synchronous inputs of the first and second triggers being the synchronizing input of the node, and the information inputs are connected with zero potential tire The 5 nodes, the setup inputs of the first and second triggers and the information inputs of the third and fourth triggers form a group of inputs for the node mode, the reset inputs of the third and fourth triggers are connected respectively to the outputs of the first and second elements AND-OR, the first inputs connected respectively to direct outputs n of this and the sixth trigger and the first inputs of the third and fourth elements 5 AND-OR, the second inputs from the first to the fourth, the inputs of the first and second elements AND-OR, the first inputs from the first to the fourth elements AND form the group of synchronizing inputs of the node, the third inputs of the third 0 and the fourth elements AND-OR are connected to the permitting input of the node, and the fourth inputs are respectively with the direct outputs of the first and second triggers, the inverse outputs of which are connected respectively 5 but to the synchronous third and fourth triggers, reset inputs connected respectively to the outputs of the first and second elements AND-OR, and inverse outputs - respectively with the reset inputs n 0 and sixth triggers, the installation inputs of which are connected respectively to the outputs of the first and second elements A, the first and second inputs of the fifth element And are connected respectively to inverse 5 outputs of the sixth and fifth triggers and the second inputs of the first and second elements AND, the third inputs of which are connected respectively to the direct outputs of the third and fourth triggers, the first and second inputs of the OR element are connected respectively to the third and fourth inputs of the fifth element L direct the outputs of the third and fourth triggers and the second inputs of the third and fourth elements And the outputs 5 of which and the inverse output of the third trigger form the fourth group of outputs of the node, the outputs of the fifth element AND of the element OR form the first group of outputs of the node, the inverse outputs of the third and fourth element AND-OR are the third and second outputs of the node respectively, the direct output of the third element The AND-OR and inverse output of the first trigger form the second group of outputs of the node, the inverse output of the second trigger and the direct output of the fourth element AND-OR are the first output of the node. 4. Device pop. 1, characterized in that the mode setting node contains a delay element, a trigger, two AND elements and two OR elements, with the synchronous input of the trigger being the synchronizing input of the node and through the element connected to the first inputs of the first and second elements And, the second inputs of which are connected respectively to the direct and inverse outputs of the trigger, which together with the outputs of the first and second elements And form a group of outputs of the node, the first inputs of the first and second elements OR are connected respectively to the outputs of the first and the second And elements, the second inputs of the first and second OR elements, and the trigger data input form a group of node state inputs, and the outputs are the first and second node outputs, respectively. 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