SU1392571A1 - Computer-to-telegraph communication channel interface - Google Patents

Description

(21) 4138684 / 24-24

(22) 10/22/86

(46) 04/30/88. Bul Number 16

(72) L. Yu. Nikolaev and L. E. Alekhin

(53) 681.325 (088.8)

(56) USSR Copyright Certificate No. 760075, cl. G 06 F 13/10, 1978.

USSR Author's Certificate No. 826332, cl. G 06 F 13/20, 1979.

(54) DEVICE FOR CONNECTING COMPUTATIONAL MACHINE WITH TELEGRAPH CHANNELS OF COMMUNICATION

(57) The invention relates to computing and can be used, for example, in automated control systems for entering information from communication channels. The aim of the invention is to improve the reliability of the device. This effect is achieved by introducing into the scheme a block of 3 keys that passes parallel input codes for writing, and a request analysis block 14 that stores the current readiness status code of the input channels at the moment of interruption or reading. Before each reading from memory block 10, the computational mask allows analyzing the number of ready-made codes in input channels, keeping time to write these codes to memory block 10, based on that number, and then proceed to the reading mode from memory block 10. ti. Therefore, the read and write modes are separated. 1 h. item f-ly, 6 ill.

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The invention relates to a computer calculator and can be used, for example, in automated control systems for entering information from communication channels when superimposing recording and reading modes.

The aim of the invention is to improve the reliability of the device. In this case, the computer is given the opportunity to analyze the state of the input channels before each reading from the memory block, maintain the time for writing information to the device, and then switch to the reading mode from the device to the computer, therefore, the reading and writing modes are separated. Thereby, an increase in the reliability of the device is achieved.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - matching unit with communication channels; in fig. 3 - priority block; in fig. 4 - block analysis of the array of information; in fig. 5 - computer matching unit; in fig. 6 - block analysis of requests.

The device (Fig. 1) includes a block 1 matching with communication channels, a group of 2 outputs of signals "Ready receiver, block 3 keys, block 4 priority, generator 5 clock pulses, block 6 counters, information switch 7, element OR 8, switch 9 addresses , memory block 10, information array analysis block 11, interrupt request output 12, computer coordination block 13, query analysis block 14, read output 15, query status output group 16, mode output 17, address comparison block 18.

The communication channel matching unit 1 (Fig. 2) includes telegraph parcel receiving units 19 | -19 ", consisting of an input key 20, a shift register 21, a shaping counter 22 shift pulses, a shift pulse counter 23 having a control input 24, an AND element 25, and a clock generator 26.

Block 1 works as follows.

A sequential telegraph code is fed to the input of the key element 20, which serves to decouple and bring the input signal to a logic level. From the output of element 20, the information code goes to the first input of register 21, as well as to the first input of counter 22, which starts working after the start bit of the information code arrives and generates shift synch pulses from the clock frequency sent to its second input from the generator 26 output. The shift pulses from the first output of the counter 22 are fed to the second input of the register 21, having recorded the code, and also to the first input of the counter 23, which performs the counting of the shift pulses under the control of the signals arriving at the input 24. After counting about definiteness of shift pulses corresponding pol5

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by receiving the information code, on the output of the counter 23, a parallel code is formed, the necessary bits of which enter the input of the AND 25 element. The AND 25 element generates the signal "Receiver readiness, arriving at the output of block 1, as well as the control input of the counter 22 to terminate the count before the next start bit arrives.

The priority block 4 (Fig. 3) consists of AND-NOT elements 27: - 27n, elements 28 | - 28 „-1 delay, elements AND 29i-29 -1, element OR NOT 30.

With simultaneous availability of information on several inputs of the priority block 4, information on its output during the cycle is fed only over one wire. Block 11 analysis of the array of information (Fig. 4) consists of encoders 31, each of which includes the elements AND-NOT 32-35, the first - the fourth elements OR 36-39, the fifth element OR 40, two triggers 41, 42, driver 43 pulses, and the element OR 44.

The array of information analysis block 11 forms four array states: "There is no information," There is information, "Information 3/4 (memory is 75% full)," Information 1. The signal at the output of AND-HE element 32 corresponds to the "Information No, and at the output of the element AND- NO 35 - the state of "Information 1. The output signals of the elements AND-HE 33 and 34 characterize the state of" Information is and "Information 3/4. The code combinations coming from the encryption nodes 31 to the output of the block 11 form the code of the state word of the information array.

The computer matching unit 13 (FIG. 5) consists of a trigger 45, control shaft 46 and address fault 47 connected to the computer, keys 48 of the fourth group, address register 49, decoder 50, keys 51 of the first group, buffer register 52, keys 53 p of the group, the information zone 54 connected to the computer, output 55 of the deflector 50, element OR 56, keys 57 of the second group, output 58 of the descrambler 50, trigger 59, keys 60 of the sixth group, output 61 of the deflector 50, element 62, item NO 63, keys 64 of the third group, buffer register 65, keys 66 of the eighth group, output 67 decoder the torus 50, OR gate 68, the output 69 of the decoder 50, keys 70 and seventh group element and 71.

If there is a signal at the input 12 on the preparation of information for reading in the computer, the trigger 45 is set to "1. This computer signal on input 46 allows information on address bus 47 to pass through keys 48 of the fourth group to address register 49, as a result of which decoder 50 switches keys of the first group 51, writes information of block 11 to buffer register 52, and simultaneously flushes trigger 45 Then the decoder 50 through the element OR 68 switches the keys of the 53rd group of the group, and the information from the buffer register 52 is copied to the computer via the information bus 54. Then, with the change of address on the address bus 47 from the output 55 of the decoder 50 through the element OR 56 the signal "H The output arrives at output 15, keys 57 of the second group simultaneously switch, and information about the number of requests at a given time from block 14 is copied to the buffer register 52, after which it enters the computer via the keys of the fifth group on the information bus 54. Received block 14 on the number of ready-made codes, the computer withstands the specified time required to write these codes to memory block 10, and then prepares the transition to the "Read, set to" 1 trigger 59 on the output 69 of the decoder 50. In this case, the recording new codes in the memory unit 10 at the time of reading therefrom.

Then the computer sets the address of the read word of the memory block 10 to the information bus 54 and writes this address to the buffer register 52 via keys 60 of the sixth group. Then, following a command from the output 61 of the decoder 50, the switches 70 of the seventh group receive the address 9 addresses and in address comparison block 18. At the same time, the signal "Reading through the OR element 56 at the output 15 is generated and the keys 64 of the third group are switched through the AND 62 element. Switching is possible, because at the moment of blocking of the keys of the block 3, the output of the HE 63 element is" 1. The information from the memory block 10 is written into the buffer register 65, and from there via the information bus 54 to the computer via the switched keys 66 of the eighth group 53 of the fifth group with a control signal from output 67 of the decoder 50.

At this point, the first reading cycle from block 10 of memory in the computer is completed, followed by another one, similar to the previous one.

After overwriting the information from block 10 to the computer, a command is received on output 69 of the decoder 50, the trigger 59 is nullified and the keys of the block 3 are unlocked. The query analysis block 14 (FIG. 6) consists of elements AND 72 | -72l, element OR 73, element 74 delay, register 75 read and write.

Block 14 is designed to record parallel codes formed from signals "Ready receiver, coming from outputs 2 of block 1 matching.

The recorded codes are sent over to the computer through the matching unit 13 to the computer for analyzing the number of codes ready to be sent to the storage unit 10 (FIG. 1).

Writing codes in block 14 takes place under the control of pulses arriving at its

inputs from outputs 12 or 15. Thus, information on the number of requests (g ones of receivers) at the moment of interruption is written to register 75. 2 Register 75 updated

after each cycle of census information from the device to the computer. To do this, in block 14 a delay element 74 is inserted, connected to its input with an output of 15 "Read device.

 Thus, after each reading cycle, a delayed pulse arriving at the input of the element OR 73 allows the entry of the input code from the outputs 2.

The device works as follows. 5 As the serial telegraph code is transformed into a parallel block 1 of matching with channels, a corresponding signal is received: Receiver readiness on one of the outputs of group 2 to the information inputs of the 3 key block, and on 0 information inputs of the information switch 7 - the parallel code of the received message with the number sign communication channel. The 3 key block in the “Record” mode passes the signals “Readiness of the receiver 5 to the inputs of the priority block 4”. At the outputs of priority block 4, single pulses appear according to the trigger priority. The counters of block 6 count the number of characters prepared for writing in memory block M, for each of the communication channels and 0 they form a code on their outputs, c. This is the address at which this entry is to be made.

At the moment, the control signal is present only on one of the equalizing inputs of the switch 9 address;) 5 (higher priority). Under its influence, the address switch 9 skips the write address corresponding to the given channel to the PA inputs of the current address of the memory block 10. As a result, the incoming information is recorded in a certain area of the memory block 10. As the array of information accumulates in memory block 10, block I 1 of the array of information analysis generates at its outputs a code of the state word of the array of each direction, and output 12 generates a 5 "Interrupt request signal in b, 1 co 13 computer coordination and analysis block 14 requests, while the request analysis block 14 generates a parallel positional code about the number of telegraph messages converted by block 1 that need to be recorded at a given time.

The computer, by processing the interruption request, determines by the word code of the array of information that the prepared information is read from block 1 (memory 1). If this is necessary, the computer sends the corresponding address to the matching unit 13, under control,

which, from block 14, from group of outputs 16 is read into block 13 and further into a computer, the status word of the number of requests at a given time.

In this case, the switching of keys of block 3 prohibits, which stops writing the converted messages to the memory block 10, and the computer proceeds to reading information from the memory block 10. To do this, at the outputs of the reading address of block 13, the code of the readable memory cell is set, and the signal "Read at output 15 reads information in the computer through block 13.

When the read address matches the write address contained at the outputs of block 6 of the counters, block 18 compares the address and gives a reset signal to the initial state of only that message counter whose readings match the current address of the read information array.

Claims (2)

1. A device for interfacing a computer with telegraph communication channels, comprising a matching unit with communication channels, a clock generator, a priority block, a counter block, an address comparison block, an array of information analysis block, an information switch, an address switch, a memory block computer matching unit and an OR element, the inputs of the matching unit with communication channels are connected by the device inputs for connecting to the telegraph communication lines, and the rpyrnia information outputs of the matching unit with communication channels are connected to information switchboard information inputs, the group of outputs of which is connected to the group of information inputs of the memory unit, the write and read inputs of which are connected respectively to the output of the OR element and the reading output of the computer matching unit, the group of information inputs of which are connected to the group of information outputs the memory unit, the address input group of which is connected to the address switch outputs, the first and second information input group and the address switch control input group are connected according with the outputs of the block of counters, the outputs of the reading address of the computer matching unit and the information outputs of the priority block, the information outputs of the priority block are connected to the counting inputs of the block of counters, the control inputs of the information switch and the inputs of the OR element, the outputs of the block of counters are connected to the first group of information inputs of the address comparison block and a group of information inputs of an array of information analysis block whose output groups are connected respectively to a group of installation inputs of a counter block s and array input group 0 0 0 5 d 50 55 computer matching unit, the read output of which is connected to the gate inputs of the address switch and address matching block, the second group of information inputs of which are connected to the output address group of the computer matching block whose synchronous input is connected to the priority output of the priority block whose synchronous input is connected to the output of the gene the clock of the clock pulses, the output of the request for interruption of the block of analysis of the array of information is connected to the interrupt input of the computer matching unit, the group of inputs / outputs of which is a group of input and output data and control for connecting to a computer, characterized in that, in order to increase the reliability of the device by separating read and write modes, a key block and a query analysis block containing a group of AND elements, an OR element, an element delays and the write-read register, in the query analysis block, the outputs of the elements AND of the group are connected to the inputs of the register of reading and reading, the first inputs of the elements of the AND group are connected to the output of the OR element, the first input of which is connected to the output of the element delays, in which the output of the interrupt request block of the array of information analysis and the read output of the computer matching unit are connected respectively to the second input of the OR element and the input of the delay element of the query analysis block whose write-read register outputs are connected to the input group of the request state of the matching block with a computer whose mode output is connected to the control input of the key block, whose outputs are connected to the information inputs of the priority block, and a group of readiness outputs of the receiver of the coax unit asovani communication with channels connected respectively with the group information input key unit, and the second inputs of the AND group query analysis unit. 2. The device according to claim 1, characterized in that the computer matching unit contains two triggers, eight groups of keys, two buffer registers, an address register, a decipher, two OR elements, two AND elements and an NOT element, with the first input the first trigger, the information inputs of the keys of the first, second and third groups are connected respectively to the block interrupt request input, the block array state input group, the block request state input block, the synchronous input of the block, the element output NOT, the information inputs and control inputs four that group, the output of the first flip-flop, the outputs of the fifth and keys schestoy groups form the input data and output control unit, and the outputs of the seventh group of keys, the second flip-flop and a first OR gate connected respectively with the group address output Read} 1i, mode and read block, the outputs of the keys of the first group are connected to the inputs of the first buffer register, the information inputs of the keys of the sixth group and the outputs of the keys of the second group, the outputs of the keys of the third group are connected to information inputs of the second buffer register, the outputs of which are connected to n - formational inputs of keys of the eighth group, the outputs of which are connected to the information inputs of the keys of the fifth and seventh groups and the output of the first buffer register, and the outputs of the keys of the fourth group are connected to the address input Registers whose output is connected to the input of the decoder, the first output of which is connected to the control input of the eighth grugigy key and the first input of the second OR gate, second and third outputs of the decoder are connected respectively to first and second inputs of the second flip-flop, the fourth output 2b R 0 The deflector is connected to the control inputs of the keys of the first group and the second input of the first, the fifth output of the decoder is connected to the first input of the first element OR, the first inputs of the first and second elements And, the cesta and the seventh outputs of the decoder are connected respectively to the second input of the second OR element and control The lower inputs of the keys of the group's group; the eighth output of the decoder is connected to the second input of the first OR element and the control inputs of the keys of the second group; the output of the element is NOT connected to the second inputs of the first and second elec ENTOV And, as the first and second outputs of AND gates are respectively connected with the control inputs of the keys of the third and seventh groups, the output of the second OR gate connected with the control inputs of the fifth group of keys. fsH R Z3 25 ..J Sn 6tfX. ) For 1lot6) di .. {from bl.6) Howl (n5l 6) You/. (K 8l. 1b) / A- bl. 13) Feedm 3x. (0f7 block 6} 12 12 about- 73 15 Editor A. Makovska Order 1809/54 Compiled by G. Sternnn Tehred I. VeresKorrektor G. Reshetnik Circulation 704Subscribe VNIIPI USSR State Committee do inventions and discoveries 1 13035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4  3 КЭ5П 5 / s (cb.18} 75 / (5l / j Ria. 6