SU1363224A1 - Device for interphasing computing with communication channels - Google Patents

Abstract

The invention relates to computing and can be used in telecommunication computing systems. The purpose of the invention is to increase speed. The device contains switching node 1, encoder 2, buffer memory 3, channel switching control decoder 4, address decoder 6, counter 5, three trigger 7, 8, 10, decoder 15, channel page counter 12, counter 14 channels, five elements And 9, 11, 16, 19, 20, element OR 13, group 18 of control registers, group 17 elements I. 4 Il. with S (L di with tSD rf :) N

Description

one

The invention relates to computing and can be used in telecommunication computing systems.

The purpose of the invention is to increase the speed by reducing the time of information transfer.

FIG. 1 is a block diagram of the device; in fig. 2 - message length in pages contained in the buffer memory (a) and exchange mode in the control registers (b); in fig. 3 - time diagram of the device; in fig. 4 is an address decoder circuit.

The device contains switching node 1, encoder 2, buffer memory 3, channel switching control decoder 4, counter 5, address decoder 6, triggers 7 and 8, element 9, trigger 10, element 11, channel 12 pages counter, element OR 13, a counter of 14 channels, a decoder 15, an element of AND 16, a group of elements of AND 17, a group of control registers 18, elements of AND 19 and AND 20, and device inputs and outputs (buses) 21-27.

The address decoder contains a counter of 28 pages of memory, a decoder of 29 pages of memory and a counter of 30 page lengths.

The switching node 1 is used to connect the communication channels to the encoder 2 in the modes of receiving and transmitting information. The encoder 2 is designed to convert the message bits to clock pulses from counter 5. Buffer memory 3 is used to store the exchange information presented in page form.

The decoder 4 control switching channels controls the operation of the node 1 in accordance with the signals from the trigger 7 and the counter 14 channels. Counter 5 generates clock pulses at the inputs of encoder 2 and address decoder 6, and sets the page length by generating signals for switching trigger 10. Address decoder 6 is used to connect the necessary page of the buffer memory. The trigger 7 generates a signal to set the device operation mode "Receive. The trigger 8 is used to generate signals to allow clock pulses to pass through element 9 at the arrival of a corresponding signal from the computer on bus 25. And element 9 controls the passage of clock pulses from the clock source to the input bus 24. Trigger 10 serves to generate signals allowing the passage of clock pulses through the element 11 and through the element 16. The element 11 is designed to control the passage of the clock pulses to the input of the counter 5. The 12-page channel counter serves to form a signal to complete the polling of each of the registers

18, if the length of the message in the pages transmitted to the communication channel is equal to the size of the corresponding control register, i.e., with the full use of all the channel memory pages.

The element OR 13 is used to assemble the signals taken from the counter of 12 pages of the channel and from the element AND 20. The counter of the 14 channels serves to form the codes of the numbers of the polled registers 18

0

or channel number codes and

five

generating a signal for completing the exchange of information over all communication channels supplied to the zero input of the trigger 8. The decoder 15 converts the counter code 14

 channels in the unitary code, thus providing the connection of the corresponding register 18 of the control group for polling pulses from the clock source through input 24, AND 16 and the corresponding element

0 and 17.

Element AND 16 serves to control the passage of pulses from element 9. The group of elements AND 17 is intended to control the passage of polling pulses to the input of the corresponding control register 18 of the group, determined by the enable signal at one of the outputs of the decoder 15. The control register group 18 provides storage information about the length of messages in the pages,

Q stored in buffer memory. The number of control registers is equal to the number of communication channels. Element And 19 is used to generate a pulse in the case of polling the bits of the control registers 18, in which units are recorded, and Element 20 is used to generate a pulse in the case of polling the first bit of each of the control registers 18 to which zero is written.

The device works as follows. Each of the group of control registers 18 corresponds to a specific number.

0 communication channels, i.e. the control register number in the group is the same as the corresponding channel number, and each unit positioned position has a specific page in the buffer memory 5 ™

When recording information about the exchange mode, a code defining the exchange mode of the respective communication channels is recorded in each of the control registers 18.

0 If, for example, in the buffer memory 3 there are H pages for each of the K communication channels, then the number of control registers must be K, the size of each control register H, each of the control registers 18 allocated by node 1 as belonging to exchange mode only in one channel. Considering that the length of the messages in the pages is transmitted through various communication channels.

can be arbitrary, the number of consecutively written units in each of the control registers can also be arbitrary.

The operation of the device begins with the arrival of a signal from the computer at the input 25, which translates the trigger 8 into the unit state, and the element 9 is unlocked and passes the clock pulse to the elements 16 and 11. In the initial state

position bits of the control register.

If in the process of shifting information bits in a control server, a positional bit appears in its output, in which zero is recorded, then an output appears at the output of AND 20, which zeroes the counter 12 and through the OR element 13 enters the counting 14 channel counter input. At the same time at the discharge outputs

the corresponding unitary code consisting of "1 on splint 12 and" O for the rest25

the state of the device, all counters zeroing the counter of channels of the channel are binary, trigger 10 is in the zero junction code of the second control register, it also blocks the passage of clock which is converted by the decipher 15 to pulses through the element 11 to counter 5, but permits their passage through element I 16 to the second entrances of the element. output busbars decoder 15. cops And 17 groups. Reset to zero - This is how the transition to the interrogation of the second counter of channels 14 is carried out corresponds to the normal control register, the left code combination for its bit e-transition to the interrogation of the next register

The control outputs, which is fed to the control inputs, are also performed in the case of the deflector 15. The zero code combination of detection of units in all positions at the input of the decoder corresponds to the 20-bit bits of the corresponding register-unit code on its outputs, consisting of the control board. In this case, at the exit from the unit level on the exit splint G1 of the decimator and zero levels on the other output wounds. At the same time, the element AND 17 of the group, connected with the thickness G1 of the decimator 15, is unblocked, and the clock pulses arrive at the first shift input of the control register of the first channel. Each clock pulse shifts the bits in the control register. As a result, the value of the sequence bits of the AND 17 group recorded in the register is unblocked by the corresponding control. At the same time, from its output, the corresponding pulses start to flow to the corresponding inputs of elements 19 and 20. The second shift input of the control register, if a position-next channel is detected. In this way, the entire bit in which the unit is written is polled, the control registers 18 and at each output of the AND 19 element appears, the channel sends messages containing a pulse (the output of the AND 20 element contains the specified pages of the buffer memory.

After the reception of information from the communication channels to the buffer memory 3, as well as in the transmission mode, the counter of the 14 channels generates a pulse at the output of the overflow, which enters the zero input of the trigger 8, sets it to the zero state, forming signal "Readiness at zero flush of this trigger. Node 1 disconnects the communication channels from the tab 2, and the trigger 8 blocks the passage of clock pulses through the AND 9 element. Thus, the polling of the transfer pages.

The 12-channel counter of the channel produces an overflow signal, which through the OR element 13 enters the 14-channel counter input, which counts this pulse. As a result, the value of the code combination at the bit outputs of this counter changes, which, in turn, leads to the appearance of a single level at the next output bar; this appears because the "1" at the inverse of this element leads to the appearance of on his way out). The following changes occur in the device.

The address 6 decoder connects the corresponding page of the buffer memory to the encoder 2. The trigger 10 is set to one state, while the passage of clock pulses through the AND 16 element to poll the next position bits of this control register is blocked. Element I 11 is unlocked, the clock pulses 45

recorded in the control registers 18, and the generation of the signals necessary for this in this device is provided to trigger the input to the counter 5 and the cipher 10, the element 11, the counter 12, the detector 2 performs the conversion of the bits of the channels, the element OR 13, the counter corresponding message page. After the page conversion is completed, the counter 5 generates a signal which is fed to the input of the trigger 10 and switches it to the zero state. The entry-55 of FIG. 3. The pulsing of the impulses to the input of the counter 5, the pre-Connecting of the necessary pages, is scanned, through the AND element 16 of the pulse memory to the tweeter 2, the signals are received to interrogate the following, the decoder 6 addresses.

14 channels, decoder 15, elements AND 16, 17, 19 and 20. The described process of polling the transfer pages is explained in the time diagrams shown in

position bits of the control register.

If in the process of shifting information bits in a control server, a positional bit appears in its output, in which zero is recorded, then an output appears at the output of AND 20, which zeroes the counter 12 and through the OR element 13 enters the counting 14 channel counter input. At the same time at the discharge outputs

the channel counter is formatted with the binary code of the second control register number, which is converted by the decryptor 15 into the output output buses of the decoder 15. This is how the transition to the second control register is polled.

the corresponding unitary code consisting of "1 on bus 12 and" O on the remaining channel counter forms the binary code of the second control register number, which is converted by the decryptor 15 in the output busbars of the decoder 15. Thus, the transition to the second control register is polled , The transition to the survey of the next register

control is also performed in the case of detection of units in all positional bits of the corresponding control register. In this case, the output P unlocking the corresponding element And 17 groups. In this case, the clock pulses begin to flow to the first shift input of the control register of the alternate channel. Thus, all control registers 18 are polled and messages are sent to each channel containing adan pages of the buffer memory.

The 12-channel counter of the channel produces an overflow signal, which through the OR element 13 enters the 14-channel counter input, which counts this pulse. As a result, the value of the code combination at the bit outputs of this counter changes, which, in turn, leads to the appearance of a single level at the next output bar by decipher 10, And 11, counter, 12 channel pages, Element OR 13, and the counter of FIG. 3. Connection of the required pages of channel 14, decalfinder 15, elements AND 16, 17, 19 and 20. The described process of polling the transfer pages is explained in the time diagrams given in

Address decoder works as follows.

A single pulse at the output of the element 19, appearing when interrogating a single positional bit of the corresponding control register 18, switches the trigger W into a single state and is counted by the channel page counter. In accordance with this, the binary code changes on the bit outputs of this counter, increasing by one, which is equivalent to increasing by one the page number of the buffer memory. This code is converted by the decoder 29 into a unitary code at its output, i.e., a code with a unit level. In the time diagrams (Fig. 3) the case is given when the number of communication channels (control registers).

Claims (2)

Invention Formula A device for coupling the computer to the communication channels, comprising a switching node, an encoder, a buffer memory 10, a circuit switching control decoder, a counter, two triggers, an address decoder, the first AND element, the first information input and output of the switching node are input and device output for connecting to channels on the bus corresponding to the country-15 communication number, the first information input and buffer memory slots to be connected to the encoder 2. The transition of the trigger 10 in the single state leads to the unblocking of the element 11. the stroke of the buffer memory is the input and output of the device for connecting respectively to the information output and input of the computer, the first input The clock pulses are received through the first 20 of the first element I and is the input of the output of the counter 5 to the input of the counter 30 of the page length and are counted by this counter. Accordingly, the output of the counter 30 forms the binary code of the addresses of the buffer memory cells within the page. Pieces for connecting to the clock output of the computer, the zero and single inputs of the first trigger are the inputs of the device for connecting to the write and read outputs of the computational maturity of the counter 30 equal to the length of the page 25, respectively, the single input and the buttons. The decoder 4 control switching channels controls the connection channels of the switching node 1 in the receive mode and the left output of the second flip-flop is the input and output of the device for connecting respectively to the output and the readiness of the computing machine, while the zero output of the first co-ordinator trigger. Channel switching takes place 0 Dinen with the enable input of the decoder in the following cases: with full use of all pages of channel memory; when determining the end of the transfer of memory channel pages by polling a zero position bit in the corresponding register control circuit switching, the output of which is connected to the control input of the switching node, the second information input and output of which are connected respectively to the first information control, which leads to the output and input of the encoder, the second impulses at the output of the element 20. 20. Formation input and output of which soy In the first case, an overflow signal is generated at the output of the counter 12 pages of the channel, which through the element OR 13 enters the input of the counter 14 channels, which leads to the formation of the binary code of the number of the next channel on the bit outputs of this counter. This code is fed to the input of the circuit-switched control decoder 4, which provides Dineny, respectively, with the second information output and the input of the buffer memory, the address input of which is connected to the 40 output of the address decoder, the first information input of which is connected to the enabling input of the encoder and the output of the counter, characterized in that, in order to improve speed, a page counter is entered into it channel counter channels. switching the channel in accordance with the post 45 third trigger, decoder, four AND elements, OR element, group of control registers, AND group of elements, and the information inputs of the control registers of the group form the device group of inputs for connecting to the computer’s address output group, with a single the output of the second trigger is connected to the second input of the first element AND and the first inputs of the second and third elements AND, the second inputs of which are connected to the output code. In the second case, the channel switching procedure by the channel switching control decoder 4 is similar. Only the formation of the binary code of the number of the next channel on the bit outputs of the 14-channel counter occurs as a result of the arrival at its input of a pulse from the output of the AND 20 element through the OR 13 element. AT And, the element OR, the group of control registers, the group of elements AND, and the information inputs of the control registers of the group form a group of device inputs for connecting to the group of address outputs of the computer, while the single output of the second trigger is connected to the second input of the first element And the first inputs of the second and the third elements And, the second inputs of which are connected to the output mode of reception, this device - with control registers of the group - synchronizes in the same way as in the transmission mode. The switching of the node I to the reception is carried out using the trigger 7. the inputs of which are connected to the outputs of the corresponding elements AND of the group, the first inputs of which are connected to the corresponding time diagrams (Fig. 3) show the case when the number of communication channels (control registers). Invention Formula A device for coupling the computer to the communication channels, comprising a switching node, an encoder, a buffer memory 10, a circuit switching control decoder, a counter, two triggers, an address decoder, the first AND element, the first information input and output of the switching node are input and device output for connecting to channels 15, the first information input and output of the buffer memory are the input and output of the device for connecting respectively to the information output and the input of the computer, the first input the first element And is the input of the device for connecting to the clock output of the computing machine, the zero and single inputs of the first trigger are the inputs of the device for connecting to the write and reading outputs of the computational small output of the second trigger are input and output of the device for connecting respectively to the output and the input computer availability, while the zero output of the first trigger is connected to the enable input of the decoder control circuit switching, the output of which is connected to the control input of the switching node, the second information input and output of which are connected respectively to the first information output and input of the encoder, the second information input and output of which are connected respectively to the second information output and input of the buffer memory, the address input of which is connected to the 40 output of the address decoder, the first information input of which is connected to the enabling input of the encoder and the output of the counter that, in order to increase speed, a channel page counter, a channel counter have been entered into it. 45 third trigger, descrambler, four ele45 Third trigger, decoder, four ele50 And, the element OR, the group of control registers, the group of elements AND, and the information inputs of the control registers of the group form a group of device inputs for connecting to the group of address outputs of the computing machine, while the single output of the second trigger is connected to the second input of the first element And and the first inputs of the second and the third elements And, the second inputs of which are connected to the outputs of which are connected to the outputs of the corresponding elements And groups, the first inputs of which are connected to the corresponding outputs deshi RATOR, the group of information inputs of which is connected to the group of information inputs of the decoder of the control of channel switching and the group of bit outputs of the channel counter, the counting input of which is connected to the output of the OR element, the first input of which is connected to the output of the third AND element and the setting input of the channel page counter whose output connected to the second input of the OR element, the output of the second element AND is connected to the counting input of the channel page counter, the second information input of the address decoder and the unit input ohm of the third trigger, the unit output of which is connected to the first input of the fourth element I, the output of which is connected to the counting input of the counter, the overflow output of which is connected to the zero input of the third trigger, the zero output of which is connected to the first input of the FIFTH element And, the second input of which is connected to the output of the first element And the second input of the fourth And, the overflow output of the channel counter is connected to the zero input of the second flip-flop, the output of the fifth AND element is connected to the second inputs of the AND elements of the group. but 1st channel 2nd for cash there is infor Nazi no information Register 1 Rvist number 2 (PU8.2 ABOUT about ABOUT about Register No. FIG. Fy pages