SU1068927A1 - Information input device - Google Patents

Abstract

A DEVICE FOR INPUT OF INFORMATION, containing a shift register, the outputs of the first group of which are connected to the inputs of the decoder, the outputs of which are the outputs of the first group of device, characterized in that; that, in order to improve speed and simplify the device, a demodulator, a single pulse shaper and a counter are entered into it, the first demodulator output is connected to the first input of the shift register, the second input of which is connected to the output of the single pulse shaper, the first input of which is connected to the first input counter and the second output of the demodulator; the inputs of which are the device group inputs, the second inputs of the single pulse generator and the counter are device inputs, the counter outputs are connected to the third and fourth inputs of the shift register, respectively, whose output is connected to the decoder input, and the outputs of the second shift register group are outputs of the second group devices .. 05 00 co vl

Description

The invention relates to computing and can be used in devices for receiving, converting and transmitting discrete messages in the form of a code according to GOST 18977-73. Various transceiver devices are known that are based on the conversion of parallel and sequential codes having "multi-channel communication lines {. However, these devices are used only. In systems where there are no strict requirements for the data transfer rate, and parallel data transfer requires a large number of elements and connections. The closest to the invention is a device containing a shift register, the outputs of the first group of which are connected to the inputs of the deshifrarator, the outputs of which are the outputs of the first group of device 2. The disadvantage of this device is circuit and hardware complexity, due to the large number of registers and connections. Using this device at an increased transmission rate reduces the reliability of the device and the reliability of the information. The aim of the invention is to increase the speed and simplify the device. The goal is achieved by the fact that a demodulator, a single pulse generator and a counter, the first demodulator output terminal are connected to the input device containing the shift register, the outputs of the first group of which are connected to the inputs of the decoder, the outputs of which are the outputs of the first group of the device the first input of the shift register, the second input of which is connected to the output of the single pulse generator, the first input of which is connected to the first input of the counter and the second output of the demodulator, the inputs to These are the inputs of the device group, the second inputs of the single pulse generator and the counter are connected and are the device input, the counter outputs are connected to the third and quarter 1m inputs of the shift register, the output of which is connected to the descramble input, and the outputs of the second group of the shift register are the second outputs device groups. FIG. I shows the functional layout of the information input device; in fig. 2 shows an example of a technical implementation of a demodulator; in fig. 3 is an example of the technical implementation of a single pulse shaper; in fig. 4 - example of the technical implementation of the counter; in fig. 5 is an example of a technical implementation of a shift register; in fig. 6 is a timing diagram of the operation of the device for receiving information. The device for entering information (Fig. 1) contains inputs of group I, demodulator 2, shaper 3 single pulses, counter 4, shift register 5, decoder 6, outputs of the second group 7, outputs of the first group 8, input 9. Input signals represented The 32-bit words in the form of successive codes, the bits of which are bipolar pulses, arrive at the inputs of group 1 to the inputs of demodulator 2. There is a mandatory pause between words. The pulses in the code of the word, and the clock pulses can be asynchronous (Fig. 6, a, e). Demodulator 2 (Fig. 2) has two outputs: the first is informational (code, Fig. 6, d) the second is synchronizing (Fig. 6, c). From the first exit issued od; nopolar rectangular pulses of duration -I-, where T is “-; F is the frequency of following bipolar pulses. The unit corresponds to an impulse with a high level of voltage, zero to a low level. From the second output, clock pulses are output with a period T in the form of a meander. For each input code pulse (each bit), one meander is issued simultaneously (32 in total). At the time of the pause between words there are no pulses at the outputs of block 2. Demodulator 2 is made, for example, on a 75AP002 microcircuit (T53.430.004 TU): The information output of the demodulator 2 is connected to the first input of the shift register 5, and the synchronizing output one to the first input of the imaging unit 3 single pulses. Blocks 3-6 of the device are made on IC chips of the type 112ТМ1 (KO.347.077.TU) - dynamic trigger with diode logic at the input; I2LD1 (GKO.347.077.TU) - OR diverter; 104ND4 (I92.222.001. TU) - the extender along AND, which are designated D, Y, Z, respectively (Fig. 3-5). (In the following, under the word "trigger, both the IC 112TM1 itself and the data chip are connected with the AND, and OR expanders connected). The shaper 3 single pulses (Fig. 3) provides for the issuance of a single pulse (Fig. 6, h) for each input (information) pulse, on the one hand, coinciding in time; positive half-wave meander, coming from the clock output of the demodulator 2, and on the other hand, synchronous with the clock pulse arriving at the second input. Former 3 from the bus 9 pulses. The imaging unit 3 is configured with a trigger for storing an input pulse, a trigger for delaying a clock pulse, a trigger for cutting off subsequent pulses, and a trigger for issuing a single pulse. The output of the driver 3 is connected to the second input of the shift register 5 for gating the bit pulses from the demodulator 2 and to the first input of the counter 4 to erase the information in it. In counter 4 (FIG. 4), performed on triggers in a ring circuit, the number of clock pulses next to the period — and arriving at the second input (counting) during the pause between words — is counted. In the absence of a pause, i.e. in the presence of sync pulses at the second output of demodulator 2, the first sync pulse generated at the output of demodulator 2 erases the information in counter 4, i.e. It does not give the counter the opportunity to dial a code corresponding to the normalized pause duration. When reaching, with a pause of 4T duration and when the contents of counter 4 correspond to this pause, counter 4 (using the output stage on three triggers) ensures that a signal is output from the first output (FIG. 6, e) allowing the code to be written from converter 2 to register 5 The "Record firing" signal arrives at the third input of register 5, in which a code message is received, for a duration equal to 32T. Simultaneously with the issuance of a sigal "Recording resolution from the second output of counter 4, a signal is output (Fig. 6, g), synchronous with a clock pulse and equal in duration, arriving at the fourth input of register 5 and recording to one in the form of a unit, after register 5 is ready to enter and write the next 32-bit word. The shift register 5, executed, for example, on series-connected dynamic triggers, consists of information and address parts. During the reception of the code, the address part is a continuation of the information. The code is entered into register 5 and written to it with a shift by means of pulses arriving at its first, second and third inputs. The first sync pulse generated after a pause between words produces a single pulse by shaper 3 and zeroes the contents of counter 4. This and subsequent single pulses initiate bitwise input and code shift in register 5. Each time the code bits shift, a shift occurs at the same time. recorded unit. After all 32 bits of the word are written to the shift register 5, the unit in the register filling process (Fig. 6 and), is shifted to the output, provides a signal from register 5 that allows the address of the received word to be decoded in the decoder 6. After decrypting the information in the form of a parallel code taken from register 5, it is ready for use in the respective receivers of the system. Consider a specific example of the operation of the device. The external sensors receive 32-bit word codes in the form of bipolar pulses from the inputs of group 1 to demodulator 2. Powering up the device may occur in the middle of a 32-bit sequential code, for example, during a 20th-bit arrival. The demodulator -2 divides the bipolar pulses from the 20th to the 32nd bit into two types: unipolar rectangular pulses (information) arriving in register 5, and the clock pulses in the form of successively following square wave, from the 20th to 32nd) arriving at shaper 3 and counter 4. Similarly, demodulator 2 converts the following (from 1st to 32nd bit) words. The former 3 generates single and ylcy, by which the given word is written and shifted in bitwise into register 5. Due to the fact that counter 4 allows writing sequential code to register 5 only after a pause (duration not less than 4T) ,. writing bits (20-32) in the register 5 does not occur. After the arrival of the last 32nd bit of a word, there is a pause until the next word arrives, fixed by counter 4, which at the moment of pause counts clock pulses. When the counter 4 is filled, it records the unit in its first bit through the fourth input of the shift register 5, while the remaining bits of the register 5 about || Next, counter 4 generates a write enable signal arriving at the third input of register 5, while the counter is zeroed and remains in this state until the next pause between the words arrives. The serial code from the 1st to the 3rdyst bit comes from demodulator 2 to the first input of register 5 and when a single pulse coincides (the second input of the register) under the condition of passing the enable signal (the third input of the register) it records 1 -th bit of a code into a register and a simultaneous shift of its unit. Similarly. the 2nd and subsequent words up to the 32nd bits are written into the register and a further shift of the unit leading the code and the bits of the code itself. As soon as the .32-bit word is written to register 5, the unit is pushed out of the register into the decoder 6 and initiates its operation. In the 32-bit code recorded in the register, the first 8 bits contain the address of the subscriber to whom the address information, and the next 24 bits - the actual information.

The decoder 6 performs the decoding of eight bits, and in accordance with the result of the decryption, the corresponding information from the remaining 24 bits of the register is copied into the receiver selected by the decoder by means of a parallel code.

Thus, a device employing sequential codes, by generating single pulses and counting the duration of not the words of the 32-bit codes themselves, but the pauses between words, is greatly simplified in terms of the number of elements, it has a fundamental novelty of structure.

When simultaneously receiving and converting information, repeatedly synchronizing the input of each word bit ensures reliable and reliable operation of the device at a high transmission rate.

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Claims (1)

DEVICE FOR INFORMATION INPUT, containing a shift register, the outputs of the first group of which are connected to the inputs of the decoder, the outputs of which are outputs of the first group of the device, characterized in; that, in order to improve performance and simplify the device, a demodulator, a single pulse shaper and a counter are introduced into it, the first output of the demodulator is connected to the first input of the shift register, the second input of which is connected to the output of the single pulse shaper, the first input of which is connected to the first input counter and the second output of the demodulator; the inputs of which are the inputs of the device group, the second inputs of the single pulse generator and the counter are the input of the device, the outputs of the counter are connected respectively to the third and fourth inputs of the shift register, the output of which is connected to the input of the decoder, and the outputs of the second group of the shift register are outputs of the second group of the device. . ', /. fig 1