SU1322344A1 - Device for transmission and reception of digital information - Google Patents

Abstract

The invention relates to the field of technology for the transmission of digital information over wired communication lines and can be applied in telecontrol systems, tele-alarm systems, and tele-data collection. The device makes it possible to increase the functional reliability and informativeness of the reception of the transmitted information by tightly linking the edges of the cycle synchronization pulse to the moments of the end of the previous and the beginning of the next transmission cycle of information on the transmitting side and reliable cycling of the cycle synchronization code containing two zero bits from the codes transmitted parcels on the receiving side. The device includes on the transmitting side 1 two multiplexers 2, 3, a generator of 6 clock pulses, a key 5, counters 4, 7, 8, elements AND 11, NOT 14. Shaper 10 IMPULSES, element 1ta OR 12, 13, transmitter 9 and sources 15 information, and on the receiving side) 7 - shift register 18, receiver 29, counters 19, 26, elements OR 24, NOT 25, driver 23, elements AND 21, 22, deshi-frator 20, key block 27, block 28 memories. The receiving and transmitting sides are connected by a wire. 1 il. (L 00 th to with 4; 4

Description

The invention relates to a technique for transmitting digital information over a wired communication line and can be used in telecontrol systems, tele-alarm systems, and in systems for transmitting coded commands.

The purpose of the invention is to increase the functional reliability of receiving information by increasing the synchronization accuracy and raising the information content due to the transmission of commands with zero address.

The drawing shows a functional diagram of the device.

The device contains on the transmitting side 1 the first 2 and second 3 multiplexer, the first counter 4, key 5, generator 6 clock pulses, third 7 and second 8 counters, transmitter 9, driver 10 pulses, element 11, first 12 and second 13 elements OR , element NOT 14, sources 15 of information, bus 16.

At the receiving side 17, the device contains the shift register 18, the first counter 19, the decoder 20, the second 21 and the first 22 elements AND, the pulse generator 23, the elements OR 24 the NOT element 25, the second counter 26, block 27 keys, the memory block 28, the receiver 29. Transmitting 1 and receiving 17 sides are connected by a link 30.

A device for transmitting and receiving digital information operates as follows.

After switching on the supply voltage on the transmitting 1 and receiving 17 sides, the counter zeroing pulses are generated. On the transmitting side 1, they are formed from the output of the imaging unit 10 through the element OR 12 to the installation inputs of counters 4 and 7. The counter 8 is folded in impulses to its installation input from the output of the generator 6 through the key 5.

At the receiving side 17, the counters 19 and 26 are zeroed by the signal generated from the output of the imaging unit 23 through the element IPI 24, and the shift register 18 with the signal from the imaging unit 23 directly. The duration of the signal formatted by shaper 23 on receiving side 17 should not

3

to exceed the duration of the signal, the three bits of the shift register 18, V

Formed by Forminontel 10 Redstey STF and-1.

After PK011PCHPIIA Ishala obiuneni on transfer1: and-and stpptsig 1 7,

That block of memory block 28, to the control input of which a signal will come from the corresponding output of the block of 27 keys, which is open and

22344 on

the input of which receives pulses from generator 6 through key 5 generates an address code at the address inputs of multiplexer 3, as a result of which the parallel information code received at the information inputs of multiplexer 3 is converted into a serial one. This code, consisting, for example, of the size of bits and containing logic zeros of the first two lower bits, is logical zeros, and in the other bits the code of a command or information about the state of an object element, comes from the output of multiplexer 3 through 15 OR 13 to the first input of the transmitter 9, to the second input of which a sequence of pulses is fed from the output of the generator 6,

The transmitter 9 converts the incoming 20 UIHC pulses to its inputs into a phase-manipulated bi-pulse signal and outputs it via the wire communication line 30 to the receiving side 17.

Receiver 29 receives this signal, 25 amplifies it and converts it into two sequences of pulses: information and clock. Under the action of the pulses of these sequences, a shift code will be written in the shift register 18, consisting of the first two bits, which contain logic zeros, and four data bits, which are connected to all information j inputs of memory block 28. containing, for example, 4p bits, where n is the number of information sources or object points. {

The clock pulses from the second output of the receiver 29 are received simultaneously - but to the input of the counter 26, which after counting six pulses forms one of the inputs of the element And 21

 signal. To the other input of the element And 21 comes an inverted clock pulse sequence. When the input signals coincide in time, the element 21 forms to control Q the l input inputs of all keys (by the number of information sources) and to the input of the counter 19 a pulse. On the leading edge of this pulse, information contained in 40 will be recorded.

nine bits of register 18 shift, V

that block of memory block 28, to the control input of which a signal will come from the corresponding output of key block 27, which is open and

313

the input of which contains the signal of the logical unit from the output of the decoder 20. Since the counter 19 was in the initial zero state, then the zero key will be opened first AND the information is recorded in the zero memory location. On the falling edge of the pulse formed at the output of the AND 21 element, the counter 19 switches to the next state. The counter 26, after counting the sixth pulse, returns to the zero state again.

On the transmitting side 1, a cyclic counter 7, each time after counting six pulses arriving at its input, generates a signal at the input of counter 4, under the action of which the latter changes the code of the address given to the address inputs of the multiplexer 2. As a result, The multiplexer 2 connects the information inputs of the multiplexer 3 in order of priority to the code signals from various information sources 15. At the end of the full cycle of the counter A, t; e. after the end of one cycle of interrogation (or transmission) of information from all n sources 15 of information at the output of an older (separate) counter 4, a logical unit signal is received that goes through the NOT 1A element to the control input of key 5 and prevents the passage of pulses generator 6 through the key 5 to the inputs of the counters 7 and 8. As a result, the counter 7 will stop, and the counter 8, on the contrary, will count the pulses arriving at its input and the output of the generator 6, since from the output of the counter 4 through the element OR 13 to the second input of the transmitter 9 IAOD signal is a logic one, and to the first input of transmitter 9 continues postu- pat pulse sequence, the transmitter 9 for a time period counted by the counter 8 will transmit a signal po- frame synchronization, corresponding to the input information yuschy (6 logical units). Counter 8, after counting six pulses, will output a signal to one of the inputs of the AND 11 element. Since at the other input of the element 11 there is a signal of a logical unit, the zero-impulse impulse will be sent from its output through the element OR to the setup inputs zero of the counter 4 and 7.

Counter 7 will be ready for the next work cycle, and counter 4, after being set to the zero state and also going to the next work cycle, will output a forbidding (zero) signal to the input of the And 11 element (And 11 will be closed), and to the input of the key 5 through the element NOT 14 - the enabling signal. As a result, the pulses from generator 6 through key 5 will again flow to the counters 7 and 8. The latest will be set to the zero state.

Element 22 is triggered on the receiving side after receiving the cyclic synchronization signal and writing six logical units to the shift register 18. At its output, a signal of a logical unit is generated, which, passing through the OR element 24, goes to, setting the zero of both counters 19 and 26 As a result, the counters are nullified (or confirm their zero state) and are ready for a new digital information receiving cycle, which is recorded (once per cycle) and stored in the cells of memory block 28. From the outputs of block 28, and hence output In the device, information in a coded form can be transmitted to various executive and receiving nodes: recording, mapping, transcoding, digital conversion, and the like.

Thus, the introduction of two counters and OR NOT elements on the transmitting side of the second multiplexer, and the AND, OR, NOT, on the receiving side of the shift register of the second counter, will NOT allow, firstly, to increase the functional reliability of receiving the transmitted information by providing rigidity linking the edges of the pulse cycle synchronization (and its reliable decoding) and the introduction of two zero bits, secondly, to ensure the possibility of transmitting zero commands and, thirdly, to ensure the transmission of digital information ( and the presence of tunable clock pulses reiiepaTnpa) without schematic change or selection of elements in a wide range of speeds (frequencies), since in the proposed ycTpoiici to generate all stnp signals in

tied to one clock source - clock pulse generator.

Claims (1)

Claim Formula A device for transmitting and receiving digital information containing information sources on the transmitting side, the outputs of which are connected to the corresponding first inputs of the first multiplexer, the second inputs of which are connected to the corresponding outputs of the first counter, a pulse driver, the output of which is connected to the first input of the first OR element, clock generator pulses, the output of which is connected to the first key input, the element I, the transmitter, whose code is connected to the communication line, on the receiving side, the device contains U receiver, whose input is connected to the communication line, And element, memory block, nepBhiii counter, whose outputs are connected to the corresponding inputs of the decoder, the outputs of the memory block are device outputs, characterized in that, in order to increase the functional reliability receiving information and informativeness by transmitting commands with zero address, the second and the third counters, the second OR element, the second multiplexer, the NOT element, the outputs of the first multiplexer are connected to the corresponding inputs of the second multiplexer; th multiplexer, second SEC) d1 which are combined and connected to ground, the output clock generator Cpd) 5en to the first inputs of the transmitter and vtorog the first input of the element AND whose output is connected to the second input of the first element 45 OR, the output of the first element Editor S.Pekar Compiled by V. Borodin Tehred L.Oliy Kkorrektor L.G.Tilipenko Order 2868/48 Circulation 543Subscription VPIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production - shkhpig rafichesky predpp and gie s, Uzhgors d, Project., 4 0 five 0 five 0 five 0 five OR is connected to the first inputs of the first counter and the third counter, the first and second outputs of which are connected respectively to the second input of the first counter and the corresponding third inputs of the second multiplexer, the output of which is connected to the first input of the second OR element, whose output is connected to the second input of the transmitter, the output of the first the counter is connected to the second inputs of the first OR element and the AND element, and through the element is NOT connected to the key input, the output of which is connected to the second inputs of the second and third accounts On the receiving circuit, the shift register, pulse generator, second counter, second AND element, NOT element, OR element and key block, pulse shaper output are connected to the first inputs of the OR element and the shift register, the second input of which is connected to the first input. receiver, the second output of the receiver is connected to the third input of the shift register, the first input of the second counter and is NOT connected to the first inputs of the first and second elements AND through the element, the output of the first element AND is connected to the second input of the IL element The output of which is connected to the first input of the first counter and the second input of the second counter, the output of which is connected to the second input of the second element I, the output of the SECOND element I connected to the second input of the first counter and the first inputs of the key block, the second inputs of which are connected to the corresponding outputs of the decoder, the outputs of the key block are connected to the corresponding first inputs of the memory block g) the shift register outputs are connected to the corresponding second inputs of the first AND element and the memory block.