SU1675948A1 - Device for restoration of clock pulses - Google Patents

Abstract

This invention relates to instrumentation engineering and can be used in magnetic storage devices. The purpose of the invention is to simplify the device. After at least one clock pulse has arrived, the binary counter 13 is set to the state corresponding to the number of counting pulses that have arrived during the duration of the clock pulse, thereby connecting via the multiplexer 18 a corresponding output of the shift register 17 to its serial input. As a result, an annular shift is made in advance of the code 16, which has been inserted by the code generation unit, of the code 0111 ... 11 during the arrival

Description

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counting pulses. Pulses corresponding to the beginning and end of the recovered clock are output to the inverse output of multiplexer 18, which are converted into a recovered clock pulse at trigger 15, the duration of which the invention relates to instrument engineering and can be used in magnetic storage devices.

The purpose of the invention is to simplify the device while maintaining the accuracy of clock recovery.

The drawing shows the functional diagram of the device.

A device for clock recovery contains drivers 1 and 2 signs of the beginning and end of information, the first trigger 3, the first element AND 4, the element OR 5, the output bus 6, the driver 7 clock pulses, the element 8, the second element AND 9, the generator 10 pulses , the third element of the AI, the prohibition element 12, the counter 13, the second and third triggers 14 and 15, the code generation unit 16, the shift register 17, the multiplexer 18.

The formers t and 2 signs of the beginning and end of information are connected to inputs S and R of trigger 3, respectively, connected by their output to the first inputs of elements AND 4 and 9, the outputs of which are connected to the first and second inputs of the element OR 5, respectively, and output 6 of which the output of the device, the output of the clock generator 7 is connected to the second input of the element 4, the input of the element 8, the installation input to the o-flip-flop 15, to the input for the enable signal of the multiplexer 18, to the first input of the element 11, This, with the counting input of the trigger 14 and the enable input of the parallel loading of the shift register 17, the inputs of the parallel data download of which are connected to the outputs of the code forming unit 16, the output of the pulse generator 10 is connected to the forward input of the prohibition element 12, and the second input of the And 11 element whose output connected to the counting input of the counter 13 and the second counting input of the register 17, the first counting input of which is connected to the output of the prohibition element 12, and the serial input connected to the forward output of the multiplexer 18, 1 - whose inputs dineny with the counter output 13, input deprecated equal duration after coming to the device clock, and the duty cycle is equal to two on the output device used passes a clock pulse, and in its absence - the recovered clock pulse to flip-flop 15. 1 yl.

in which O is connected to the input of the installation in O of the trigger 14 and its output, the inverse output of the multiplexer 18 is connected to the counting input of the trigger 15, the output

which is connected to the third input element And 9, the second input of which is connected to the output element NO 8.

The principle of operation of the device is based on the fact that after the arrival of at least one clock pulse, the binary counter 13 is set to the state corresponding to the number of counting pulses that arrived during the duration of the clock pulse, thereby connecting via

multiplexer 18 is the corresponding output of the shift register 17 to its serial input. As a consequence, an annular shift is made in advance laid down by the code generation unit 16.

01111 ... 111 at receipt of counting pulses. Pulses are output to the inverse output of multiplexer 18, corresponding to the beginning and end of the recovered clock pulse, which are converted on the trigger 15 to the recovered clock pulse, the duration of which corresponds to the duration of the last clock pulse arriving at the device. In this case, the duty cycle of the recovered clock pulses is equal to two. A clock pulse passes to the output 6 of the device, and in its absence a recovered clock pulse from trigger 15. Moreover, pulses to output 6 of the device will pass only if there is a gate from trigger 3, the time of which is determined by signals from drivers 1 and 2 signs of the beginning and end of information . If there is no new clock pulse on the device on its leading edge, the counter 13 is zeroed and then filled to such a state that corresponds to the duration of this clock pulse. Shaper 1 can be built on the principle of counting a certain number of pulses reproduced from one of the information tracks in a given direction of carrier movement without tracking pulses from the shaper 7, Shaper 2 sign of the end of information can be built on the principle of counting the rows (clock pulses) contained this array of information.

The device works as follows.

On the basis of the beginning of information from the driver 1, the trigger 3 is set to one state and the enable signal from its direct output goes to the first inputs of the AND 4 and 9 elements. A clock pulse from the driver 7 clock pulses through the elements A A and OR 5. In the absence of clock pulses at the output of the device b, the recovered clock pulses from the direct output of the trigger 15 through the elements AND 9 and OR 5.

On the leading edge of the first clock pulse coming from the clock clock generator 7, a short pulse is set at the counter 14 on the shaper 14. During a clock pulse, And 11 passes a certain number of pulses from the pulse generator 10 to the counting input of the counter 13 which counts them and gives the result to the inputs of the selection of modes of the multiplexer 18. The multiplexer 18 is gated on the input for the enable signal E by a clock pulse, after which one of the 1 inputs of the multiplex and is connected to the output of multiplexer 18. The input Number l-determined state of the counter 13.

The code generation unit 16 provides a constant output to the inputs of the parallel loading of the register 17 for the first bit O, for the rest of the bits 1. A clock pulse is used as the enable signal for the parallel loading, which is supplied from the output of the clock maker 7 to the input of the RE register. Parallel recording is carried out on the falling edge of the pulse from the generator of 10 pulses transmitted to the second counting input of the shift register 17 through the element 11 during the time of the clock pulse.

After the end of the clock pulse, the first counting input of the shift register begins to receive pulses from the generator output 10 pulses through the prohibition element 12, shifting the recorded code. In this case, a unit from the forward output of the multiplexer 18 is recorded in the lower bits of the shift register 17 via a serial input.

After a certain number of pulses, equal to the number of pulses counted by counter 13, a zero value appears at the forward output of multiplexer 18, which will again be written to the first digit of the shift register. At the same time, at the inverse output of multiplexer 18, a single pulse appears, which determines the beginning of the recovered clock

0 pulse. In the absence of a clock pulse, the cyclic shift continues and the inverse output of the multiplexer 18 will form a second single pulse corresponding to the end of the reconstructed

5 clock pulse. Pulses corresponding to the beginning and end of the recovered clock pulse on trigger 15 will be converted into a recovered clock pulse, the duration of which

0 corresponds to the duration of the last clock pulse that came to the device from the driver 7 clock pulses. The cycle is repeated until the arrival of a new clock pulse.

5Print of new clock pulse

ensures that trigger 15 is set to O, counter 13, the lower register of the shift register 17 is O, and the rest is 1. Next, the counting and minimization of the number of pulses by the counter 13, the cyclic shift and the formation of the recovered clock pulses continues.

On the basis of the end of information trigger

Claims (1)

5 3 is zeroed out, prohibiting the passage of received clock or recovered clock pulses to the output b of the device, Formula of the invention A device for recovering clock pulses containing a formate. Are there signs of the beginning and end of information the outputs of which are connected respectively with installation inputs in 1 and in o first a trigger whose output is connected to the first inputs of the first and second AND elements, whose outputs are connected via the OR element to the output bus, a clock pulse generator whose output is connected to the second input of the first AND element, through the NOT element to the second input of the second And element with the installation input in O of the second trigger, the output of which is connected to the third input of the second element I, the pulse generator, the output of which is connected through the third element I to the counter input of the counter, the third trigger, characterized in that, in order to simplify device with preserving the accuracy of the restoration of clock pulses, entered into the shift register, multiplexer, 7 16759488 information inputs of which are connected to the multiplexer rarefaction input, are connected to the corresponding outputs of the third input element I, the inverter, and mode selection inputs are connected to the input of the inhibiting element, counted by the corresponding counter outputs, the input of the third trigger, and the redirection input the code generation unit, the outputs of which are parallel to the loading of the shift register, is connected to the corresponding input-output of the pulse generator is connected to parallel data loading to the direct input of the prohibition element, the output of the shift register hectare, and a prohibition element, the third trigger is connected to its input which is connected to the first counting reset and the counter reset input, the counting input of the shift register, the second counting 10 input of the second trigger connected to the inverse input which is connected to the output of the third multiplexer output, the direct output of which element And, at the same time, the output of the fortior is connected to the serial input of clock pulses connected to the shift register.