SU1509992A1 - Device for digital magnetic recording - Google Patents

Abstract

The invention relates to the accumulation of information, namely to a technique of digital magnetic recording. The purpose of the invention is to improve the accuracy of digital magnetic recording (clock sync pulses) by decreasing undesirable combinations of the repetition of individual symbols in the recorded information. The device contains a master oscillator 4, two elements 3 and 5, two delay elements 6 and 7, a shift register 9, a static register 8, a memory block 10, a trigger 1, a magnetic recording apparatus. New is the introduction of multiplexer 14, counter 13 and the third element And 12.

Description

one

(21) 4389640 / 24-10

(22) 01/05/88

(46) 09/23/89. Bul No. 35

(72) V.N. Vasiliev, Yu.S.Gerasimov,

G.M. Solodikhin and V.V. Zotov

(53) 681.84.001.2 (088.8)

(56) USSR Author's Certificate 1195381, cl. G 11 B 5/09, 1984.

USSR Author's Certificate fr 1270788, cl., C 11 B 5/09, 1985.

(54) DEVICE FOR DIGITAL MAGNETIC RECORDING

(57) The invention relates to the accumulation of information, namely to the technique

digital magnetic recording. The purpose of the invention is to improve the accuracy of digital magnetic recording (clock sync pulses) by decreasing undesirable combinations of the repetition of individual symbols in the recorded information. The device contains a master oscillator 4, two elements 3 and 5, two delay elements 6 and 7, a shift register 9, a static register 8, a memory block 10, a trigger 1, a magnetic recording apparatus. New is the introduction of multiplexer 14, counter 13 and the third element And 12. 1 sludge.

SP

about with

The invention relates to the accumulation of information, namely, devices for digital magnetic recording.

The purpose of the invention is to improve the accuracy of digital magnetic recording.

The drawing schematically shows a device for digital magnetic recording,

The device contains a trigger 1 connected by an output to an input of a recording unit 2, for example, a magnetic recording apparatus, and connected by an input to an output of a first IZ element connected by a first input to a first output of a master oscillator 4, a second element I 5, the first and second elements 6 and 7 are delays, a static register 8, a shift register 9, and a memory block 10. The second output of the master oscillator 4 is connected to the first input of the second element 5, connected by the output via the first delay element 6 to the sync input of the static register 8. The second delay element 7 is connected by output to the clock input of the shift register 9 connected by the information input to the input bus 11, connected to the first address input of the memory unit 10. The latter is connected by the first group of address inputs to the outputs of the shift register 9, connected by the second group of address inputs to the outputs of the static register B, and connected by outputs to the information inputs of the static register 8.

The device also contains a third element AND 12 connected by an output to the second input of the second element AND 5, a counter 13 connected to the second address input of the memory unit 10 and connected by an input to the second output of the master oscillator 4 connected to the input of the second delay element 7, and a multiplexer 14 connected by an output to the second input of the first element I 3. In this case, the outputs of the static register 8 are connected to the channel inputs of a multiplexer 14 connected by address inputs to the other outputs of the counter 13 connected to s third AND 12.

The device works as follows

In the initial state, all bits of the counter 13, the static register 8 and the shift register 9 are zero.

, p 5 o

0

five

0

therefore, the zero binary symbol from the first bit of the static register B through the multiplexer 14 is supplied to the recording unit 2 by means of the first And 3 element and the trigger 1.

In the first cycle of operation, the binary signal of the digital information is recorded in the first bit of the shift register 9 with the information shifted in the remaining bits on the clock signal of the master oscillator 4. The clock signal of the master oscillator 4 does not pass through the second element 5 to the first delay element 6, since at the output of the third element And 12 there is a low potential. The clock signal of the master oscillator 4 changes the state of the counter 13, which provides the connection of the second channel input of the multiplexer 14 to its output. The latter ensures the arrival in block 2 of the record through multiplexer 14 of the signal from the second bit of the static register 8.

In the second cycle of operation, the counter 13 is transferred to the state in which the zero character is read from the third bit of the static register 8 through the multiplexer 14 into the block 2 of the record,

In the third cycle of operation, the counter 13 is transferred to the state in which the zero character is read from the fourth bit of the static register 8 through the multiplexer 14 into the block 2 of the record. When the input bus width 11 is four, the single states of the first two bits of the counter 13 provide a high potential at the inputs of the third And 12 element, which opens the second And 5 element to pass the clock signal from the master oscillator 4 to the sync input of the static register. 8, As a result, a permission is prepared to record the output combination of binary signals from the memory block 10 instead of the previous zero combination of binary signals,

In memory block 10, information is stored of two matrices of Latin squares, a feature of which is the interdependence of their information contents. At the same time, in each of the matrices in two rows and in two columns, combinations of binary signals are placed with the formation of the full code in each row and column.

In the fourth cycle of operation, the signal at the sync input of the static register 8 provides a record of. its combination is characterized by a two-argument function of the zero matrix. In this case, the number of the matrix used determines the content at the moment of time of the information of the third bit of the counter 13,

The fifth, sixth and seventh work cycles occur similarly to the first, second, and third work cycles, respectively. In the eighth cycle of operation in the static register 8, the combination of the third bit of the counter 13 is determined by recording the combination, which determines the use of the working matrix every four clock cycles. Therefore, then everything repeats with the provision in the twelfth cycle of operation of writing into the static register 8 a combination characterized by a two-argument function of the zero matrix.

Thus, using the invention in the recorded digital information eliminates the regular repeatability of symbols of the same type, which contributes to increasing the reliability of the recorded information with interference and spurious effects inherent in the magnetic recording process.

Claims (1)

Invention Formula A device for digital magnetic recording containing a trigger connected by an output to the input of a recording unit and connected to the entrance, exit lane. And connected to the first output of the master oscillator, the second output of which is single-key to the first input of the second element, And connected to the output through the first delay element with the sync input of the static register, Q the second delay element connected by the output to the synchronization input of the shift register connected by the input to the input bus connected to the first address input of the memory g, which is connected by the first group of address inputs to the outputs of the shift register is connected by the second group of address inputs to the outputs static register and connected to the outputs of the information inputs of the station five 0 five For example, in order to improve the accuracy of a digital magnetic recording, a third And element is inserted into it, connected by an output to the second input of the second And element, a counter connected by an output to the second address input of the memory unit and connected by an input to the second the output of the master oscillator connected to the input of the second delay element and the multiplexer connected by the output to the second input of the first element I, and the gains of the static register connected to the channel inputs of the multiplexer are connected th address input to the other counter outputs connected to the inputs of the third element I.