SU1270788A1 - Device for performing digital magnetic recording - Google Patents

Description

one

The invention relates to a magnetic recording technique, namely to devices for digital magnetic recording.

The purpose of the invention is to record the recording density by transcoding digital information.

The drawing shows the functional diagram of the device for digital magnetic recording,

A device for digital magnetic recording contains a master oscillator 15 connected by a first output to the input of the first delay element 2, shifting the register 3, connected by an information input to the input bus 4, a static register 5 connected by the outputs to one address - memory block 6 inputs second element 7 delay, trigger 8, connected to the output of the apparatus 9 magnetic recording. In addition, the device for digital magnetic recording contains the first and second elements 10 and 11, the first of KOTOptjx is connected by inputs to the first and second outputs of the master oscillator 1 and the output through the second delay element 7 -. to the interconnection of the synchropist system, to the input of the static register 5, and to the control inputs of the static and shift registers 3 and 5, with the master oscillator 1 being connected to the first input of the second element H II by a first output. connected to the output with the input of the trigger 8 and the BTOpbDvi input with the output of the last bit of the shift register 3; the connected output of the remaining bits to the other address inputs of the memory block 6 connected by the first of the address inputs to the input bus 4, the control input to the second output of the master oscillator 1 and the outputs to interconnected informational inputs of the static and shifted: 1st registers 3 and 5, while the first delay element 2 is connected to the synchronization output by the output. its input is shift, its register is 3,

The device works in the following way.

In the initial state, trigger 8, registers 3 and 5 are zeroed, and in block 6, in rows and columns, multi-bit combinations of binary signals are placed according to the selected matrix of the Latin square, t 6. in each

07882

The combination of a row or column forms a complete code.

On the first cycle of operation, the binary signal of digital information from the bus 4

S is written to the first bit of register 3 with a delay relative to the clock signal of oscillator 1 for the time specified by delay element 2. Before that, directly on the clock

 The signal of the generator 1 from the last bit of the reistor 3 is read through the second element 11 of the binary signal of the digital information to the counting input of the trigger 8, and from the last to the device 9 of the magnetic recording.

On subsequent cycles, the process of the device operation is halogenous to the first cycle. Before the n-th cycle in register 3 recorded (n-1) binary signals of the input digital information. Registers 3 and 5 are designed for n bits of binary information, and block 6, respectively, 2n address inputs. : At the cycle of operation of the device, the clock signal from the second output of the generator 1 from block 6 reads the memory cell specified by the row addresses - (n-1) bits of binary signals from the register

 3rd and nth bit binary bit

input digital information from bus 4 and column (this is the zero n-bit of the combination of binary signals of register 5), read out of block 6 of the national binary signals by a parallel code is written to registers 3 and 5 as a result of simultaneous supply of a delayed clock signal to their synchronization and control Yunday input. The delay time of the clock signal is determined by the delay time of reading the information from block 6. At the same time, the clock signals from the first and second outputs of generator 1 pass the first element 10 and the delay element 7 successively on every second cycle. The delay time of a clock signal in delay element 2 is equal to the total delay time of a circuit of elements 10 and 7.

As with (n-l) -x, preceding clock cycles directly on the clock signal from the first output of the generator

Claims (1)

55 1 through the second .element 1 1 is read from the last bit, register 3 is a binary signal of digital information LiHH. Thus, the device 9 is magic and after the n cycles of operation of the device enters the positive code from register 3 of the zero binary signals. In subsequent cycles of operation of the device, the process is accordingly repeated. At the same time, through the trigger 8, the device 9 comes from register 3 in the sequential code previously read into register 3 from block 6 of the null combination. In addition, it is also used by register 5 as the address of the column when polling block 6 (the current combination of the input digital information serves as the address of the row). Based on the corresponding content of the Latin square matrix information stored in block 6, the recorded digital information is eliminated by the regular repetition of symbols of the same type, which contributes to increasing the stability of the recorded combination in terms of interference and parasitic effects inherent in the magnetic recording process. For reliable operation of the device, clock signals are supplied to the control outputs of the registers 3 and 5 (respectively, from the first and second outputs of the generator 1). When there are no clock signals on these inputs, polling of registers 3 and 5 is impossible. During the reproduction of digital information, the matrix of the Latin square, which was used in advance when recording, performs the reverse procedure and thereby uniquely restores the original information. 884 The claims of the device for digital magnetic recording, comprising a master oscillator connected by a first output to the input of a first delay element, a shift register connected by an information input to an input bus, a static register connected by outputs to one address input of a memory block, a second delay element A trigger connected to the output of a magnetic recording apparatus, characterized in that, in order to increase the recording density by recoding the frame synchronization, the first and second elements are inserted into it And the first of which is connected by inputs to the first and second outputs of the master oscillator and the output through the second delay element to interconnected synchronization input of the static register and control inputs of the static and shift registers, and the master oscillator is connected to the first output of the second element And connected by the output to the trigger input and the second input to the output of the last bit of the shift register connected by the outputs of the remaining bits to the other address inputs of the block and the memory connected by the first of the address inputs with the input width, the control input with the second output of the master oscillator and the outputs with interconnected information inputs of the static and shift registers, while the first delay element is connected with the output to the synchronizing input of the shift register.