SU1324036A1 - Device for solving systems of algebraic equations - Google Patents

Abstract

The invention relates to computing and can be used in specialized computing devices to solve systems of algebraic equations of the form. The aim of the invention is to improve the speed of the device. For this purpose, the device contains a matrix of computational elements, structurally similar to the coefficient matrix A (a-;. Each computational element processes one of the unknown systems using a tabular computation method using two fixed memory blocks. Calculations are performed in a redundant quaternary number system. 1 Cp f-crystals, 4 ill. With b with N3 N O oo o:

Description

The invention relates to computing and can be used in specialized devices designed to solve systems of algebraic equations of the form.

The aim of the invention is to improve the speed of the device.

On. shows the block diagram of the device; Fig, 2 is a functional diagram of the computing element; in fig. 3 - time diagram of the device; in fig. 4 - functional synchronization block diagram.

The device contains a group of registers 1 unknown, a group of registers 2 arrests, a group of registers 3 increments, an element OR-NOT 4, a trigger 5, an element 2И-OR 6, N. groups of N computational elements 7 and a synchronization unit 8. The device has N groups of N inputs 9 of the coefficient recording, start input 10, outputs 11 and inputs 12 of the initial conditions.

Computing element 7 contains registration 13, two memory blocks 14 and 15, six delay elements 16-21 and adder 22 in the redundant quaternary number system. Computing 7 element has a control input 23, a coefficient record input 24, two information inputs 25 and 26 and exit 27.

The synchronization unit 8 comprises a pulse generator 28, a counter of 29 bits, a counter 30, a decoder 31, triggers 32, AND elements 33 and three elements OR 34-36.

Block 8 has a start input 37, a cycle reference input 38, three outputs 39-41 and a group of N outputs 42.

The device works as follows.

Let it be necessary to find a solution to the algebraic system of equations

 , (1),, b. , ..., b,

where a

 , .but.

a, a ,,.

Ml

    nn

For implementation in the proposed device, the system is represented as

fii Efi- Adhr lhr ,, (gr ,,), 1, ...,, B, lx, 0.

0

15 0

5 o

0

five

0

five

dde RD is a symbol indicating that the first most significant EI stitch bit is taken as an increment. ,

As follows from expression (2), free members are taken as the initial approximation, which are entered into registers 2 as attributes along the inputs of 12 initial conditions. The coefficients of the matrix A are entered into the registers 13 of the computational elements 7, and a .. is recorded in the j-th computational element 7. The i-th group B of the 3 increment registers initially recorded zeros. The trigger 5 is in the zero state (this is for definiteness, in the first step it does not matter what state the trigger is 5), then, by a series of control signals from output 40, the contents of the registers 3 increments of the bits after discharge start with the oldest bits, arrives at the first information inputs of 25 computational elements. Zero values of increments come from registers of 3 increments to the second information inputs of 26 computational elements. The computational element performs the operation of multiplying the coefficient of the matrix A stored in this element by the increment and addition of the product with the input element of the viscous. For an arbitrary element a-- you can write

. (i) i- + a, .lh. .J

Since in the first schag all lx are zero,, -, i.e. nezka retains the value of the free term.

Consider the procedure for calculating the background in some detail. For definiteness, we choose the number 1 flag. Thus, the most significant bit from the first register 3 goes to the first computational element (RE) of the first group. The increment, -0, comes here. The increment lx is multiplied by the high bit of the coefficient a stored in the register of the considered ET. This is done as follows. The highest bit co ||) of the a, which is represented in the quaternary redundant numbering system, goes to the first address input of the first memory block 14 from register 13. To the second address input, increment l x is received. In memory block 14, a multiplication table is recorded.

numbers of an excessive quaternary number system. Two types of coding are used here: auxiliary, containing the following digits 0,1,2, -1, and the main coding containing six digits 0,1, 2,3, -1, -2. As an example, we will show the value at the output of the memory block when the maximum digits arrive:

Here binary coding of quaternary digits is used (0-0.00, 1 - 0.01, 2 - 0.10, 3 - 0.11, -1 - 1.11, -2 - 1.1Q). Thus, after multiplying, the most significant bit arrives at the first address input of the second memory block 15, the second address input of which receives the least significant bit of the result of the previous multiplication. In our case, both inputs receive zeros. At the third input comes a bit of discharge, In block 15 of memory, a table of

bridging 3-X numbers at its inputs. The result is formed in the form of two digits, the high order goes to the adder 22 directly, and the youngest is delayed by one clock cycle. After the arrival of the second bit in the sum 22, the first bit of the result is finally formed. Thus, after two cycles, the first bit of the first partial gap is E. appears formed, and it enters the second CE of the first group.

The arrival of an older partial partial error to the information input of the indicated CE allows the formation of a new partial negative to begin. Allowing the second cell to work is accomplished by applying to the control input the computing elements of the series

pulses from the second exit group

42. This series is similar to the series from the first exit of group 42 and is shifted by bit. In the second VE of the first group, a new partial pattern is formed. VE works similarly to that described. Passing sequentially through the computational elements of the rows, partial overlap on the outputs of the last computational

five

0

five

0

35 0

five

gp

five

These lines are finally formed as a set of new nets p (eti; (C4-i) -. It happens in 2n cycles, two cases are possible 2n m and 2n ha, where m is the number of bits of the data being processed, in each case operation diagram. Figure 3 shows the operation diagram for case 2.t., In this case reading from the register registers ends before processing the matrix in the matrix. E connection with this in sync series from outputs 40 and 4 of block 8 control there is a moment when the pulses are absent (pause). The length of the first pause is determined value (2n-t). The first pause is formed when reading from the backlog register is completed, and writing is still impossible, the second pause occurs when writing to the register is completed, and reading from the backlog register is unacceptable, so How the tail of the computational elements is read from the outputs of the computational elements. After completing the multiplication, three additional clocks are needed to zero the multiplication circuit - the clock for the first group of delay lines, the clock for the BTOpiTo group and the clock for reset of the adder 22. Thus, the minimum pause time equal to tiktu. In order for the transient processes to complete completely, we extend the second pause to two cycles. Then the total computing time for the unstance will be

. (2n-m) (n + l) + m.

Consider how the increments of the unknowns are formed. From the algorithm (2). it follows that the highest bit gap is taken as an increment. The highest bit is formed by the second clock cycle at the outputs of the adders 22, the secondary EE groups. To achieve this measure, a signal is sent from. output 39 of control block 8. It coincides in time with the second impulse from the second output of group 42. According to this impulse, the higher distributions of the low discharges are recorded in the increment registers and the addition of the contents of the registers 1 of the unknown with the higher discharges of the nets. At the same time, the result of the analysis of the higher bits is not fixed to zero in trigger 5. Suppose that at least one bit is non-zero, then

Yes, there is 1 at least on one wire, and at the output of the element ITSHEE 4 there will be zero. This suggests that the iterative process of finding the current bit of unknowns is not complete and should be continued. In that case, if all the major bits are zero, the output of the element, H1I-NO 4, will be a signal equal to 1 The contents of the 1 register of the unknown are shifted towards the older rades. As a result of the shift, the younger bit of the unknown and the incoming new increment will have one weight. At the same time, the trigger 5 is set to one state and the input of the shift register 2 pulses is not w, but (m + l) impulse. As a result, not m bits, but (m + l) e Since the record is kept starting from the higher bits, the first most significant bit will be lost, and the second most significant bit will be the first. As a result of this operation, the following is achieved. All senior bits, and they were, as was shown, zero, will be excluded from the analysis. Breakdown bits that have a weight of 1 less will now be analyzed, but the number of the clock in which they will be analyzed is saved, the bit being analyzed remains first. Thus, by increasing the weight of the contents of the register of the unknown and the gap, you can save Although the transition to the search for the next lower bit was made. This process is repeated until all m bits have been determined. This is determined by counting in the control unit the number 1 generated at the output ment NOR 4,

Claims (1)

Invention Formula 1 device A device for solving systems of algebraic equations containing a group of registers of the unknown, a group of register registers, a group of increment registers and an OR-NOT element, characterized in that, in order to increase speed, it contains a trigger, an element 2И-ШШ, N the information input of the register in N by computational elements is the input of the record of the coefficient vy (where N is the number of unknowns, equal to the numeral element, the second infor the number of equations in the system), and the syn- thetic block the register input is connected to the synchronization, the cycle assignment input of which is its output and to the first address inputf5 20 g fo. 240366 connected to the output of the element OR NOT, to the information input of the trigger and to the shift inputs of the registers of the unknown group, the information input i-ro (, N) of the register of the unknown group is connected to the output of the N-ro computing element of the i-th group, q. the entry of the element OR NOT and the information inputs of the i-ro group increment register and the i-ro register register group, the output of the latter is connected to the first information input of the first computing element of the group, the second information inputs ix of the computing elements of all groups are connected to the output The i-ro group increment register, the sync inputs of the group increment registers and the unknown group registers are connected to the trigger synchronization input and the first output of the synchronization unit, the inputs of the 2I-STI element are connected to the forward output of the synchronization unit, the second and third synchronization blocks, respectively and the inverse trigger output, the output of element 2И-ШШ is connected to the inputs of the shift register registers group, the j-ro computing element (Nl) of each group is connected, to the first input (j + l) -ro of the computational element of the same group, which control inputs i-x (, N) of computational elements of all groups are connected to (i + 3) -My output of the synchronization unit group, input of the coefficient i-ro of the computational element thirty 35 The i-th group (, N,, N) is the iM input of the device’s j-th group coefficient recording input, the trigger input of the synchronization block is the device start input, the outputs of the registers of the unknown group are the corresponding device outputs, the setup inputs of the unregistered register are the inputs of the initial conditions of the device, t 2, The device according to claim 1, wherein the computational element contains a register, two memory blocks, six delay elements and an adder in a redundant quaternary interfacing system, and the synchronous input of the register is the control input of the computational element, the first memory block, the second address input of which is the second information input of the computing element, the first information input of which is connected to the first address input of the second memory block, the second address input of which is connected to the first output of the first memory block, the third whose address input is connected to the outputs of the first, second and third delay elements, respectively, whose inputs are connected to the corresponding bits of the second output of the first memory block, the first output of the second block The memory is connected to the input of the first term of the adder in the redundant quaternary number system, the input of the second term of which is connected to the outputs of the fourth, fifth and sixth delay elements, respectively, whose inputs are connected respectively to the first to third bits of the second output of the second memory block. For example, the output of the sum of the adder in an excess number system is the output of the computational element. 26 19 75 (puff. 2 J ran  ft Tr ... 4/7 4f -t 42 GZL Zji  four Compiled by N. Zaharevich Editor T. Parfenova Tehred, I. Popovich Corrector I. Muska Order 2967/53 Circulation 672 Subscription VNIIGSh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4