SU1298906A1 - Pulse counter - Google Patents

Abstract

The invention relates to automation and computing and can be used in counters, pulse distributors with increased speed and the possibility of error correction. The purpose of inventions. Increase speed and provide error correction. The device contains adder 1, cascades 6.1–6.3, each of which contains triggers 7.1–7.3, elements AND 8.1–8.3, 9, elements OR 10.1–10.3. In order to achieve this goal, elements OR 5.1–5.3 are introduced into the device, new connections in connection with an increase in the number of inputs of elements I. I. Il., 1 tab. СЛ ю с 00 со о О5

Description

The invention relates to automation and computing technology and can be used in discrete information processing devices, in particular, as counters, pulse distributors and information-encoding devices with improved speed and the ability to correct errors.

The purpose of the invention is to increase speed and provide error correction by introducing new design features.

The drawing shows a diagram of the pulse counter with and.

The counter contains an adder 1, an input bus 2, output buses 3.1-3.5 and 4 elements OR 5.1-5.3, cascades 6.1-6.3, each of which contains triggers 7.1-7.3, elements AND 8.1-8.3 and 9 and elements OR 10.1-10.3.

In each of the cascades 6.1-6.3, the direct output of the I9 element is connected to the output of the trigger 7.3 of the cascade 6.3 and connected to the inputs of the adder whose output is connected to the output bus 4, the inputs of the OR 5 element.

Dami R-flip-flops 7.1-7.3, direct wedges with direct outputs of flip-flops

moves which are connected respectively with the first inputs of the elements OR 10.1-10.3, the inverse outputs of which are connected respectively with the first

7.2 and 7.1, respectively, of the cascades 6.1 and 6.2, the inputs of the OR 5.2 element are connected to the direct outputs of the flip-flops 7.3, 7.2 and 7.1, respectively

the inputs of the elements 8.1-8.3, the outputs of the cascades 6.1-6.3, the inputs of the element OR

which are connected respectively to the inputs 5 of the trigger 7.1-7.3, the second inputs of the elements AND 8.1-8.3 are connected to the input bus 2 and to the second input of the element I9, the first input of which is connected to the direct output of the element OR 10.1; The first additional inputs of elements of AND 8.1–8.3 of cascade 6.3 are connected to the direct output of trigger 7.1 of cascade 6.2, and the third inputs of elements ,,.

35

5.3 are connected to direct outputs of three hells 7.3 and 7.2, respectively, of the cascades 6.2 and 6.3.

The operation of the proposed device we consider a specific example, with the number of bits of the counter n 5 and the control number to 3.

The code combinations of the state of the pulse counter and the stages 6.1-6.3 are given in the table.

I

00000

01100

00100

OP01

00110

from

001II

ten

and 8.1-8.3 of which are connected to the direct output of the trigger 7 .1 of the cascade 6.1, the second inputs of the elements OR 10.1-0.3 of which are connected respectively to the direct outputs of the elements AND 10.1-10.3 of the cascade 6.2, the second inputs of the elements OR 10.1-10.3 of which are connected respectively with direct outputs of elements OR 10.1-10.3 of cascade 6.3, in each of cascades 6.1-6.3 the second additional inputs of elements AND 8.1-8.2 are connected respectively with direct outputs of elements OR 10.2 and 10.3, the third inputs of elements AND 8.2-8.3 are connected to the inverse output element and 9; output buses 3.1- 3.5 are connected respectively with the direct output of trigger 7.1 of cascade 6.1, with outputs of the elements OR 5.1-5.3 and with

direct output trigger 7.3 of the cascade 6.3 and connected to the inputs of the adder 1, the output of which is connected to the output bus 4, the inputs of the element OR 5. connected to the direct outputs of the triggers

7.2 and 7.1, respectively, of the cascades 6.1 and 6.2, the inputs of the OR 5.2 element are connected to the direct outputs of the flip-flops 7.3, 7.2 and 7.1, respectively

cascades 6.1-6.3, element inputs OR

5.3 are connected to the direct outputs of the flip-flops 7.3 and 7.2, respectively, of the cascades 6.2 and 6.3.

The operation of the proposed device we consider a specific example, with the number of bits of the counter n 5 and the control number to 3.

The code combinations of the state of the pulse counter and the stages 6.1-6.3 are given in the table.

14

10101

15

10110

sixteen

11,000

10,000

17

11001

As can be seen from the sequence of code combinations of the first cascade

6.1, the filling of its bits takes place sequentially, starting with the highest bit. As soon as all its bits are filled with units, the cascade 6 is zeroed out and the transfer signal gives permission to change the state of the second cascade.

6.2, the filling of which with units also starts with the highest order. The process of filling the first cascade with 6.1 units is then repeated, starting with the penultimate bit, since the unit bits of the cascades block the introduction of units into the same bits of all previous cascades. All subsequent cascades will be filled at the transfer signal from the previous cascade.

The formation of code combinations of the pulse counter will occur on the basis of the code combinations of the stages as follows. The first and fifth bits will correspond to the first bit of the first cascade 6.1 and the highest bit of the third cascade 6.3, respectively. The second bit will be formed from the second bit of the first cascade 6.1. and from the first bit of the second cascade 6.2 combined by the logical operation OR. The third bit will be similarly formed from the third bit of the first cascade 6.1, the second bit of the second cascade 6.2 and the first bit of the third cascade

6.3, And the fourth bit will be

Table continuation

five

0

five

0

five

0

five

formed from the third bit of the second cascade 6.2 and the second bit of the third stage 6.3.

If at the output of a pulse counter a code pattern is distorted due to a code pattern distorted in one of the cascades as a result of one or several higher bits, one hundred times before any low-order bit, to the opposite state, then after one or several clock bits the pulses at the output of the pulse counter will be found in a code combination corresponding to the number of clock pulses arriving from the time of the reference point, i.e. in this case, there will be no change in the number of clock pulses for searching all the code combinations.

The counter works as follows.

In the initial state, in all stages 6.1-6.3, code combinations 000 are found. Accordingly, on output buses 3.1-3.5, code combination 00000 will be found. With the arrival of the first clock pulse on the input bus 2, the trigger 7.3 of stage 6.1 will be set to one through the element And 8.3 of the cascade 6.1, which is opened with single signals from the inverse output of the element OR 10.3 and from the inverse output of the element AND 9 of the same cascade. As a result, a code combination of 100 will be recorded in cascade 6.1.

The 51N signal from the direct output of trigger 7.3 of the cascade 6.1 enters the input of the OR 5.2 element, as a result, a single signal also appears on the output of this element, and on the output buses 3.1-3.5, the code kimbin 00100 shows respectively. direct output trigger 7.3 of the cascade 6.1 will also go to the input of the element OR 10.3 of the same cascade and from its direct output allow the next clock signal from bus 2 to pass through the element 8.2 of the same cascade to the input of the installation in the trigger unit 7.2 of the same cascade As a result, in the cascade 6.1 b children entered codeword on. A single signal from the direct output of trigger 7.2 of the cascade 6.1 is fed to the input of the OR 5.1 element and from its output to the output bus 3.2. Code output 00110 will be located on the output buses 3.1–3.5 of the counter. At the same time, a single signal from the direct output of trigger 7.2 of the cascade 6.1 arrives at the input of the OR 10.2 element of the same cascade and from its direct output will give permission to pass the next clock signal from bus 2 through the element 8.1 of the same cascade and set the trigger 7.1 of the same cascade to one state. A single signal from the direct output of trigger 7.1 of the cascade 6.1 will go to the output bus 3.1 and the code combination 00111 will appear at the output of the impulse counter. driving the clock signal from the input bus 2 to the input of the AND 9 element, triggers the 7.1-7.3 cascade 6.1 to the zero state by a single signal from the output of the AND 9 element of the same cascade, which will be opened with a single signal from the direct output of the OR 10.1 element same cascade. At the same time, a single signal from the direct output of trigger 7.1 of cascade 6.1 is fed to the input of the element I.8.3 of cascade 6.2 and will give permission to record a single signal to the trigger 7.3 of cascade 6.2. As a result, code sequence 000 will be in cascade 6.1, and 100 in cascade 6.2. The single signal from the direct output of trigger 7.3 of cascade 6.2 will go to the input of the OR 5.3 element and from its output to the output bus 3.4. Output pulse counter

five

0

five

0

five

0

five

0

55

owl code is 01000.

At the same time, a single signal from the direct output of the trigger 7.3 of the cascade 6.2 is fed to the input of the IPI 0.3 element of the same cascade and from its direct output to the input of the element OR 10.3 of the cascade 6.1 and prevents the input signal from passing through the element 8.3, the inverse output of the element OR 10.3 of the same the cascade, and a single signal from the direct output of this element will give permission for the input signal to pass through the element 8.2 to set the trigger 7.2 of the same cascade to one. As a result of the passage of a clock pulse, code combination 010 will be in the cascade 6.1, and 100 in the cascade 6.2. The output of the pulse counter is 01010.

Similarly, the cascade 6.1 will be filled up to the first bit inclusive, i.e. in cascade

6.1 the code combination 011 will be recorded, and the output of the pulse counter will be 010П. With the arrival of the next clock signal, the cascade 6 will be reset and at the same time the trigger 7.2 of the cascade 6.2 will be written to the unit. And so on. After the cascade is filled with 6.2 units at the next clock signal from the input bus 2, the cascade 6 will be reset and at the same time write to the high-level discharge of the 6.3 unit. In this case, in the cascade 6.3, the code combination will be recorded - 100, in the cascade

6.2- 000, in the cascade 6.1 - 000, and at the output of the pulse counter - 10,000. A single signal from the direct output of the trigger 7.3 of the cascade 6.3 is fed to the input of the OR element 10.3 of the same cascade and from its direct output to the input of the element OR 10.3 cascade 6.2 and prohibits the next clock signal to pass to the input of the trigger setup 7.3 of the same stage in a single state, simultaneously with the direct output of the OR 10.3 element of the same cascade, a single signal arrives at the input of the OR 10.3 element of the cascade 6.1, and prohibits the passage of the next clock signal through the AND 8.3 element same to SCADA and allow through AND gate 8.2 of the same flip-flop of the cascade unit 7.2 of the same stage in a single state. AT

7

as a result, code combination 010 is sent in cascade 6.1, and 10010 at the output of pulses, etc.

After writing in codec cascade 6.1, in the cascade 000, and in the cascade 6. the last code combination - 11100 will be generated at the output of the pulse counter. With the arrival of the next clock signal from bus 2 to the element 9 of the cascade 6.3, this cascade will be reset to - i.e., all cascades will go to the initial state - 000, and at the output of the pulse counter there will also be the original code combination - 0000

As an example, consider the recovery of information after the distortion of code combinations from the table. If the code combination at the output of the pulse counter 00110 changes after a fault on 00010 as a result of the transition - 0 in the third bit of the first cascade 6.1, i.e. the combination 110 changes to 010, then after the next clock pulse arrives on the pulse counter in the first cascade 6.1. the third and first bits will go to the unit state, i.e. code combination 111 is detected. The output of the pulse counter will be code combination 00111, which corresponds to the next code combination of the pulse counter.

If the code combination at the output of the pulse counter 11000, corresponding to the sixteenth clock pulse, changes to 01000 as a result of switching to the third bit of the third stage 6.3 (code combination 110 changes to 010), then after the first clock pulse arrives in the first stage 6.1 code combination 101 will be recorded, 000 on the second clock pulse and 000 in the second cascade 6.2 - 101. With the arrival of the third clock pulse, code combinations 000 and 000 will be recorded in cascades 6.1 and 6.2, and 111 in the cascade 6.3. impulse s for three cycles on Vits correct codeword 11100, corresponding nineteenth clock pulse, which must be error-free at the counter.

06

eight

Analogue of information will occur in the event of erroneous transitions of O-.

If the thirteen code combination at the output of the impulse counter 10100 changes to 11100 due to the distortion of the code combination 010 in the second stage 6.2 by 110, then after the first clock pulse in the first stage 6.1 the code kimbin 001 will be recorded, after the second one 000.

6.2- 111. With the arrival of the third clock pulse in cascades 6.1 6 .3, the corresponding code combinations 000, 000, 110 will be recorded. The correct code combination - 11000, corresponding to the sixteenth clock pulse will be formed at the output of the pulse counter.

The presence of adder 1 at the output of the pulse counter will allow one to continuously calculate the single bits in the code combinations of the pulse counter and, in the event that the number of units of a given magnitude is exceeded, an error signal will occur, which further increases the noise immunity of the counter.

Claims (1)

Formula invented and A pulse counter containing an input bus, an adder, n output buses and n-k + 1 cascades, where k is a check number, is less than the number n, but is greater than zero, each of the cascades contains the first bit, the state of the trigger, the first of the second AND element and the OR element whose direct and inverse outputs are connected respectively to the first inputs of the second and first AND elements, the direct outputs of which are connected respectively to the R and S inputs of the trigger, the direct output of which is connected to the first input of the OR element, the second the input of the first element and is connected to the input bus, characterized in that, in order to improve speed and provide error correction, a group of n2 elements OR is entered into it, and in each cascade from the second to the k-th bit, each of which contains a trigger, the first AND element and the OR element , the first input of which is connected to direct trigger output, input S of which is connected by the output of the first element AND, the first, second, third inputs of which are connected respectively to the inverse output of the OR element, to the input bus and to the inverse output of the second element And of the first discharge, direct output and the second the input of which is connected respectively with the inputs of the R-flip-flops of the higher bits of a given cascade and with the input bus, the direct output of the first-bit trigger of each cascade is connected to the first additional inputs of the first elements AND bits of the subsequent Cascade, direct the output of the element OR of each bit of which is connected to the second input of the element OR of the same name of the previous editor A. Kozoriz Order 898/59 Tehred M. Khodanych Corrector L Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, ul, Proektna, 4. In each cascade, the direct output of the element OR of each bit, except the first, is connected to the second additional input of the first element AND of the previous discharge, the direct output of the i-ro trigger of the j-ro cascade, where, ..., k, j 1,. . ., n-k + 1, is connected to the corresponding input of the i-fj-2nd element OR from the group of OR elements, the outputs of the OR elements of which are connected to the inputs of the adder and with the corresponding p-2 output buses, the remaining output buses are connected to the additional inputs the adder and with the direct outputs of the triggers of the first and last bits, respectively, of the first and last cascades. Proofreader L. Patay