SU1357956A1 - Sequential carry digital integrator - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can find application in numerical control systems, as well as in measuring and computing devices. The purpose of the invention is to increase speed. The device contains a control code register 1, a controlled frequency divider 2, an increment table memory block 3, shift registers 4, 5, AND 6, 8, and OR 7 elements. The goal is achieved by replacing the counting operations and adding to the shift operation. 1 il ... With JV SL O5

Description

one

The invention relates to computational and information-measuring equipment, namely, automatic control systems, and can be used in numerical, programmed control systems, as well as in measuring and computing devices.

The purpose of the invention is to increase the speed of the integrator.

The drawing shows a block diagram of an integrator.

The integrator contains the control code register 1, the controlled frequency divider 2, the memory block 3, the increment table, the first 4 and second 5 shift registers, the first element, AND 6, the OR element 7, the second element AND 8, the input 9 of the initial setup of the integrator, integrator information input 10, integrator control code inputs 11, integrator output 12, integrator write pulse input 13.

The invention implements a digital integrator based on a shift register, the law of operation of which is completely analogous to the law of functioning of a binary multiplier. For the latter, the following is characteristic:

a) the number of output pulses after the input arrivals is equal to

M-t

ent

+ T

ten

k-i

where a is the value of the manager's digits

)

code, and a;

 O or 1; when mixing pulses from the output. Duplicators of the frequency of a binary multiplier in one channel do not impose one pulse on another;

the number of output pulses of the integrator in time T is equal to

-. one

X dt

The integrator works in the following way.

The control word, determined by the number of pulses to be formed at the output of 12 integrators for 2 input pulses, is received by. 10 integrators at the second input are written to register 1 from inputs 11 at the output pulse. Older mn

The bits of the control word are fed to the inputs of block 3, where the value of a multi-bit increment is stored at the specified address, periodically repeated during the formation of a predetermined frequency-pulse sequence. Insertion pulses that are absent in periodically repeating

The Q of the frequency sequence obtained by cyclic shift of the multi-bit increment recorded in block 3 is formed by an N-bit divider 2. With the value of logical

5 zero at input 9, the high-order bit of the shift register 4 takes the value of a logical unit, and the remaining bits of the register - the value of a logical zero. When the value is logical zero

The Q at the input 9 of the integrator to the shift register 5 records the value of the information word coming from block 3. If the value of the logical unit at the input of the integrator is, the shift 5 registers 4 and 5 switch from the setting mode to the shift mode, and the shift registers 4 and 5 are executed cyclic.

So in the shift register

0re 4, the cyclic shift of the logical unit recorded in the press of the setting in the high register register, and in the shift register 5, the cyclic shift of the information word coming from the memory block 3 is carried out. Shifts of shift registers 4 and 5 coincide 1T and are equal.,

In block 3, the values of information words are stored, the cyclic shift of which ensures the formation of a frequency-pulse sequence with a given structural repeatability.

The upper M-N bits of the control word stored in register 1 define the address of the corresponding information word, the unit values of which are determined according to the expression

five

0

five

50

 )

BUT;

t)

where p 5

the bit number of the information word formed at the output of block 3; the bit number of the input control word, with 1 I corresponding to the most significant M-bit of the control word;

31

i 2 (M-1) is the control word bit, etc. (i.e., index i defines the sequence number of the control word in question relative to its highest bit);

BUT; - equal to O or 1, corresponds to the value of the i-ro bit of the input control word;

k. is the current parameter; k-1,2,3. The p-value is chosen from the interval 0 pi: iM-N. So, with the value of the control word equal to 13.5 01101, M 5, N 3, the output of block 3 forms the value 0010. The lower three bits (in this case 101) arrive at the binary multiplier, which forms the insertion pulses.

The pulse frequency on the divider 2 is less than the input frequency of the pulses fed to the input 10 of the integrator by a factor of.

The formation of the output frequency-pulse sequence is carried out by cyclically transforming the information word coming from block 3, from parallel to sequential form and adding shsuls-inserts formed by a binary multiplier at certain time instants.

Let us consider in more detail the work of the integrator on a numerical example. Let the size of the proposed digital integrator be five, i.e. M 5. Therefore, in 2 clocks, the integrator must generate a number of pulses equal to the control code supplied to input 11 and stored in register 1. For example, if control code arrives at input equal to 13, then in 32 clocks the proposed - Tegrator should generate thirteen pulses at the output 12.

The output sequence of the proposed integrator must exactly match the output sequence of the binary multiplier (sequential transfer integrator) with the same control code. Denote the presence of a pulse at a clock point in time in the output sequence by 1, and the absence of a pulse is denoted by O. The output sequence of a 5-bit binary multiplier with control code 13 has the form 001 10010001100110011001000П0010. We divide the sequence into eight groups:

OOP 0010

OOP 0010 OOP

(one)

From this it follows that these groups are identical during the first three cycles within each group. This is a feature of the operation of the binary multiplier, since the pulses in the latter are removed from the outputs of a conventional binary counter, and the pulses from the outputs of the counter are repeated at well-defined intervals. These groups, except for the pulses in the fourth clock cycle, can be reproduced by cyclically shifting the shift register of the word 0010. The pulses in the fourth clock cycle in each sequence group (1) are formed at specific time intervals.

Write in binary form the control code, equal to 13

13.0 01101 ...

The lower three bits of the control code are 101, i.e. five This means that these bits take part in the formation of five pulses. It is obvious that the older two bits provide the formation of eight pulses (RLR 8, 0).

Let us compare this with the frequency sequence formed by the binary multiplier. The pulses from 1 to 3 bars of each group are determined by the upper two bits of the control code 13. Their total number is eight. The pulses in the fourth cycle of each group are determined by the lower three bits of the control code. There are five of them (in 1, 3, 4, 5, 7 groups). This feature follows from the law of operation of the binary multiplier.

In the proposed integrator, the upper two bits of the control code (in our case 01, since 13, d 01101) come from register 1 to block 3j where the word 0010 is written at address 01. Obviously, we completely simulate the cyclic shift of the latter in shift register 5 operation of the binary multiplier from the upper two bits when the control code is 01101. In this case, in 32 cycles, i.e. for eight complete shifts of the word 0010, we get eight pulses. The lower three bits of the control code (bit 101) from register I are sent to a 3-bit binary divider that every 32 clock cycles of the input signal received at input 10 of the integrator generates five pulses, since the control code for it is equal to five. Divider 2 must form for each group of four pulses a pulse that coincides in time with the fourth pulse in group (1). Obviously, the input frequency for divider 2 must be lower than the frequency of the pulses at the input 10 of the integrator and the input of the shift register 5 by four times, since divider 2 generates one pulse for a group of four pulses generated at the output of the shift register 4. This in turn determines the size of divider 2, equal to three, since the latter forms five pulses (for the considered example) for eight groups (8 32t4).

 In order to clock the pulse formation time by binary divider 2 to the beginning of the fourth pulse, the shift register 4 and the element 8 are entered in the considered groups (1).

F O p mule invention

Digital sequential transfer integrator containing. M-bit control code register (M - control word width),

Compiled by A. Chekanov Editor L. Langazo Tehred L. Serdyukova Proofreader L. Lilipenko

6000/50

Circulation 671 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, ul. Project, 4

7956 .6

equal frequency divider, where the integrator control code inputs are connected to the information inputs of the control code register, the synchronization input of which is connected to the integrator recording pulse input, the low bits of the control code register are connected to the control inputs of the controlled frequency divider, different

so that with the aim of fasting

20

25

Actually, it contains a memory block of the increment table5, two shift registers, two zerms, an OR element, and the integrator's information input is connected to the synchronization inputs of the first and second shift registers and the first input of the first AND element whose output is connected to the first input of the OR signal whose output is connected to the integrator output, the integrator initial setup input is connected to the control inputs of the first and second shift registers, the high-order output of the first shift register is connected to the information the lower-order input of the first shift register, the first input of the second And element, and the information input of the controlled frequency divider, the output of which is connected to the second input of the second And element, the output of which is connected to the second input of the OR element, the higher-order outputs of the control code register are connected with the address inputs of the memory of the increment table, the outputs of which are connected to the informational inputs of the second shift register, the output of the higher bit of which is connected to the information input of the lower the same number of registers and the second input of the first element I.

thirty

35

Claims (1)

Claim A digital sequential transfer integrator containing an M-bit register of the control code (M bit of the control word), an equalizable frequency divider, the inputs of the integrator control code being connected to the information inputs of the control code register, the synchronization input of which is connected to the input of the integrator recording pulse, the outputs the least significant bits of the register of the control code are connected to the control inputs of the controlled frequency divider, characterized in that, with the aim of increasing speed, it contains the memory lock 'of the increment table, two shift registers, two AND elements, an OR element, the information input of the integrator connected to the synchronization inputs of the first and second shift registers and the first input of the first 2Q element AND, the output of which is connected to the first input of the OR element, the output of which is connected with the output of the integrator, the input of the initial installation of the integrator is connected to the control 25 inputs of the first and second shift registers, the output of the highest bit of the first shift register is connected to the information input of the younger row of the first shift register, 00 the first input of the second AND element and the information input of a controlled frequency divider, the output of which is connected to the second input of the second AND element, the output of which is connected to the second input of the OR element, the outputs of the upper bits of the control code register are connected to the address inputs of the table memory increments, the outputs of which are connected to information — ₄ θ information inputs of the second shift register, the output of the highest bit of which is connected to the information input of the least significant bit of the same register and the second input of the first element I.