SU1256198A1 - Frequency divider with variable countdown - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is to expand the functionality of the device. The frequency divider contains a pseudo-random sequence sensor 1, a scaling unit 2, a code comparison element 3, AND 5 and 7 elements and a trigger 6. The introduction of the code comparison element 4 and the OR 9 element allows the division factor to be changed randomly with predetermined limits. 1 il. ff with iS (L 1C ate Od CD oo

Description

The design relates to a pulse technique and can be used in automation devices and computing equipment, as well as in modeling various processes, for example, errors in communication channels.

The purpose of the invention is to enhance the functionality of the nyfeM to allow the variation of the division ratio to be randomly specified.

The drawing shows an electrical block diagram of the device

The variable divider frequency divider contains a SRP sensor 1, the outputs of which are connected to the inputs of the higher bits of the calculating unit 2 and with the first groups of inputs of the first 3 and second 4 code comparison elements, the first output of the first of which is connected to the first input of the first element And 5, the output of which is connected to the first input of the trigger 6, the second input of which is connected to the second input of the first element AND 5 and the output of the second code comparison element 4, the third input to the second output of the first code comparison element 3, output - with the first input of the second element I 7, the second input of which is connected to the input bus 8 and the clock input of the calculating unit 2, the output to the first input of the element OR 9, the second input of which is connected to the output of the crossing unit 2 and the output bus 10, output With a clock input of the sensor 1 ncnj, the second groups of inputs of the first 3 and second 4 elements of the comparison code, the setup inputs and the mode selection input of the sensor 1 are connected to the corresponding outputs of the program block 11, which is a dial pad consisting of switches,

The essence of the operation of the device is that the variable division factor is set by presetting the higher bits of block 2, the low bits of which work as a simple frequency divider, in the state defined by the state of all bits of the register of sensor 1 .. After appearing at the output of the device of the next pulse, the register of the sensor 1 is shifted and the new number is written to the higher bits of block 2, and since the period of sensor 1 is equal to 98 .. 2 is 2 −1 cycles, 2 –1 natural numbers are formed in its register numbers from 1 to 2 -1, h reduyuschihs according to a pseudorandom. The average division ratio

,

 H

1 + (2 -1)

n-1 2,.

If it is necessary to limit the maximum and minimum division factors, block 11 records the maximum and minimum numbers that determine the maximum and minimum division factors. If sensor 1 registers numbers that exceed the specified values in the register of sensor 1, then the clock input of the register sensor 1 receives additional shifting cycles, which exclude the possibility of writing forbidden combinations to block 2; Sensor 1 register is advanced by high-frequency cycles while there are signals that This number is in the code that is outside the limits for the second groups, the inputs of elements 3 and 4.

The device works as follows

In the operation mode of the device as a divider: with the specified division factor, the register of sensor 1 is set to the parallel recording of information received from block 11. Moreover, the specified division ratio is set by block 11. From the output of the register of sensor 1, information (number) in parallel forms to the block 2

In the operation mode of the device as a divider with a pseudo-randomly dividing factor, the register of sensor 1 operates in the mode. shift register.

When a single pulse on bus 10 appears in block 2, the number recorded in sensor register 1 is entered. At the same time, the pulse from bus 10 through element 9 enters the same input of sensor 1, and the input of block 2 receives a new number, numerically equal to About the next division ratio. This number is entered in block 2 after the occurrence of the next impulse on bus 10.

If, after the next advancement of the number in the register, sensor 1, in rows x, writes a number N greater than the number k, the incoming

on element 3, or less than the p number, transmitted to element 4 from block 11, element 3 (or 4) generates a pulse, which trigger 6 translates to the zero state. At the same time, element 7 opens, to the second input of which pulses are received from bus 8 of a higher frequency than the frequency of the pulses arriving at the inputs of the higher bits of block 2. With these pulses, the number in sensor register 1 begins to accelerate. As soon as the next shift in bits x, -x, the number N is smaller than the number k and greater than the number p on you during element 3, an impulse appears, by which the trigger 6 is transferred to one state, and element 7 is closed. Element And 5 blocks the pulse from the output of element 3 to the input of flip-flop 6, when a pulse appears on the spring of element 4, i.e. when number N is less than k and less than p.

Claims (1)

Invention Formula Variable frequency divider ko-30 dividing ratio, containing a scaling unit, the clock input of which is connected to the input bus, the output - to the output bus, a pseudo-random sequence sensor (PSP), outputs 35 Editor I.Shuhsha Order 4836/57 Compiled by A.Sokolov Tehred A. Kravchuk Proofreader S. Cherni Circulation 816 Subscription of the USSR State Committee for Inventions and Discoveries VNRSHPI 113035, Moscow, Zh-35, 4/5, Raushsk nab. Production and printing company, Uzhgorod, st. Project, 4 which is connected to the first group of inputs of the first comparison element, the first output of which is connected to the first input of the first element AND, the output of which is connected to the first input of the trigger, and the second element AND, characterized in that, in order to extend the functionality division factor according to a random law with given limits; an OR element is introduced into it, a second code comparison element and a program block, the corresponding outputs of which are connected to the second group of inputs code comparison element with the PSP sensor mode selection input, the outputs of which are connected to the inputs of the higher bits of the scaling unit and the first group of inputs of the second code comparison element, and with the installation inputs of the PRS sensor and the second group of inputs of the second element of the comparison codes whose output is connected with the second input of the first element And with the second input of the trigger, the third input of which is connected to the second output of the first element of the code comparison, the output to the first input of the second element And, the second input of which is connected to in discharge bus output - to the first input of the OR gate, whose output is connected to the clock input of the SRP sensor, the second input - to the output bus.