SU1358096A1 - Phase shift to speed and acceleration code converter - Google Patents

Abstract

The invention relates to the field of automation and computing and can be used to connect analog information sources with a digital computing device. In order to expand the field of application by generating an acceleration module code into a phase shift converter into a speed and acceleration code, containing reference and measuring tires, six frequency dividers, two single vibrators, three triggers, three AND elements, an OR element, a clock driver, and three formers pulses, three synchronizers, adder, register, counter, entered two registers, arithmetic logic unit (ALB), three single-vibrator, four flip-flops, two AND elements, two OR elements, a decoder and the second form irovatel clock. If there is no movement of the measuring signal relative to the reference, the number of pulses arriving at the summing and subtracting inputs of the counter is the same. With a uniform displacement of the measuring signal relative to the reference number of pulses, rewritable in two registers, the same. In the presence of acceleration, deceleration, or reverse, the number of pulses rewritten from the counter to the registers is different and proportional to the change in frequency in each reference period. At the same time, for acceleration and deceleration, the acceleration code is defined in the ALB as the difference of codes in the registers, and for the reverse, as the sum of the codes of the registers for the counting period. The maximum angular rate of phase change is half the period of the reference signal. 2 Il. c (L 00 SP ro o yu 05

Description

The invention relates to automation and computing and can be used to connect analog information sources with a digital computing device.

The purpose of the invention is to expand the field of application of the converter by generating an acceleration module code.

Figure 1 shows a block diagram of a converter; figure 2 - the timing diagram of his work.

The converter contains buses 1 and 2, respectively, of the reference and measurement signals, dividers 3-6 frequencies, one-shot 7-9, trigger 10, driver 11 clock pulses, counter 12 pulses, registers 13 and 14, arithmetic logic unit (ALB) 15, register 16, elements AND 17 and 18, elements OR 19, frequency divider 20, decoder 21, trigger 22, one-shot 23 and 24, elements OR 25, trigger 26, impulse drivers 27-29, trigger 30-32, synchronizers 33-35, elements AND 36-38, adder 39, frequency divider 40, element OR 41, pulse generator 42, shaper 43 cycles impulses. The adder 39 has outputs Sum 44 and Transfer 45. The ALB has information inputs 46 and 47 for code A and code B, respectively.

The Converter operates as follows.

The shaper 43 of the clock pulses forms two sequences of alternating clock pulses (TI1 and TI2), the duration of which is equal to the pulse duration of the generator 42 pulses, and the frequency at its outputs is twice lower than the frequency of the generator 42.

The pulses of the TI2 sequence are fed to the inputs of the synchronizers 34 and 35 and to the input of the And 36 element, and the pulses of the sequence of TI1 are fed to the inputs of the And 37 and 38 elements and to the input of the synchronizer 33. The shapers 27 and 28 form short pulses (Fig. 2c, d) the moment of input signal change (fig. 2a, b) from a negative value to a positive value, and shaper 29, on the contrary (fig. 2e), when the input signal changes from a positive value to a negative value (fig. 2b). The flip-flops 30-32, the output signal from which is fed to the corresponding inputs of the synchronizers 33-35, ensure the passage of whole pulses through the AND 36-38 elements when applying to one inputs of the flip-flops 30-32 pulses from the corresponding drivers 27-29, to their other inputs - transfer pulses from the outputs of dividers 3-5, respectively. At the outputs of the elements And 36-38 are obtained

bursts of pulses (Fig. 2e, g, h) with the number of pulses in the bursts equal to the division ratio of the divisors 3-5.

The frequency of the generator 42 pulses and the division ratio of the dividers 3-5

5 at a given reference signal frequency is selected based on the desired phase resolution discretization and time and acceleration time sample resolution.

0 signal from the output element and 36

(Fig. 2e) is supplied to the subtracting input of the counter 12 pulses. The signals from the elements 37 and 38 (fig. 2g, 3) are fed to the summing inputs of the adder 39.

5 The signal from the offHoro output 44 of the adder 39 is fed to the element OR 41 through a frequency divider 4F having a division factor of 2, and the ac of the other output 45 directly. Resultant

0 signal from the output of the element OR 41. (Fig. 2i) is fed to the summing input of the pulse counter 12 and is a sequence of bursts of counting pulses, one after the other at a pulse frequency in the bursts equal to f.

The signal (Fig. 2k) from the pulse output of the divider 3 is fed to the input of the divider 6. The pulses of the signal (Fig. 2l) from the pulse output of the divider 6 copy the sign of the counting result from counter 12 to trigger 22. Pulses from the pulse output of the divider 6 pulse frequency through the one-shot 7 comes to the shaper 11 clock pulses, which forms two sequences of alternating pulses, the duration of which is equal to the duration of the pulses from the one-wave 7, and the frequency at its outputs is half the frequency of the output pulses of the divider 6 .

five

0

five

0

These pulses arrive at the control inputs of registers 13 and 14 and overwrite the result of the counting of the differential counter 12 pulses alternately in them.

The pulses from the output of the one-shot 7 through the one-shot 8 provide

ten

15

31358096

reset to zero counter 12 pulses. Pulses from single vibrators 7 and 8 occupy the time interval between pulses ТИ1 and ТИ2.

In the absence of a change in the phase of the measuring signal relative to the reference one in any mutual arrangement (Fig. 2b), the number of pulses fed to the summing and subtracting inputs of the pulse counter 12 is the same, and the result of the counting, which is copied to registers 13 and 14, does not change. When changing the phase of the measuring signal relative to the reference (Fig. 2b), corresponding to the phase lag in the signal, from the output of the element OR 41 (Fig. 2i) this phase change corresponds to the absence of pulses, and fewer pulses go to the summing input of the pulse counter 12 than his subtracting The result of counting, rewritten into registers 13 and 14, corresponds to a phase change with an imus sign, rewritten from counter 12 to register 22 by a pulse from the pulse output of frequency divider 6

When changing the phase of the measuring signal relative to the reference, the corresponding phase advance in the signal from the OR 41 element, this phase change corresponds to twice the number of pulses (Lig.2i) and the total input of the counter of 12 pulses is 20

AP

sequentially rewritable in registers 13 and 14, are equal to each other.

In the presence of acceleration, deceleration or reversal, the result of the reading, alternately rewritten from the counter 12 pulses to the registers 13 and 14 pulses from the generator of 11 clocks, is different and proportional to the frequency deviation in each reference period.

For acceleration and deceleration, the acceleration code is defined as the difference between the codes of registers 13 and 14, and for reverse, the acceleration code is defined as the sum of the codes of registers 13 and 14 during the reference period.

The signals from the information outputs of registers 13 and 14 arrive at information inputs 46 and 47 of the ALB 15. When implementing the ALB 15 arithmetic function AB, when the code of the number from register 13 is greater than or equal to the code of the number from register 14, the information outputs of the ALB 15, the difference of codes is highlighted, and at its output- Transfer - the log level. 1. Level- log. 1 from the output The transfer enters the D input of the trigger lOj at the C-input of which a pulse arrives from the monowater 8. Under the action of this impulse, the trigger 10 is set to one state and ensures the passage of the pulse from the one-vibrator 9 through the elements AND 17 and OR 19 to upog- Lui jc I / ii. j net has a larger number of pulses, - equalizing input of register 16 and P-input

than on his subtracting. The result of counting, rewritten into registers 13 and 14, corresponds to a phase change with a plus sign, rewritten from the counter 12 pulses to the trigger 22 by the pulse from the pulse output of the frequency divider 6.

If there is no movement of the measuring signal relative to the reference number of pulses with element. com. AND 36 and OR 41, arriving at the subtracting and summing inputs of the counter 12 pulses, the same. The results of the counts in registers 13 and 14 are equal

to zero.

I

40

With a uniform movement of the measuring signal relative to the reference signal in the direction of an operative} or shrinkage in the pulse counter 12, a number proportional to the velocity of the phase of the measurement signal relative to the reference signal accumulates during the measurement time. At the same time, the trigger triggers 26. At the same time, the result is copied from the information outputs of A.P.P. 15 to register 16 and trigger 26 on the control inputs of the ALB 15, confirms its execution of function AB.

When ALB 15 implements the arithmetic function AB, when the code of the number from register 13 is less than the code of the number from register 14, the information output of the ALB 13 shows the difference of codes in the additional code, and at its output Transfer is the log level. A. At the same time, under the action of a pulse from a single-vibrator 8, a trigger 10 sets a to the zero state and ensures the passage of TI1 pulses through an element I 18 to the input of a divider 20 and to the shift inputs of registers 13 and 14. It is distributed across the decoder 21. with a divider 20 allocates pulses n and 2n at its outputs, where n is the pulse number equal to the number of register bits 13 and 14. At the time it reaches 50

55

five

0

WITH

sequentially rewritable in registers 13 and 14, are equal to each other.

In the presence of acceleration, deceleration or reversal, the result of counting, alternately rewritten from the counter 12 pulses to the registers 13 and 14 pulses from the generator of 11 clocks, is different and proportional to the frequency deviation in each reference period.

For acceleration and deceleration, the acceleration code is defined as the difference between the codes of registers 13 and 14, and for reverse, the acceleration code is defined as the sum of the codes of registers 13 and 14 during the reference period.

The signals from the information outputs of registers 13 and 14 arrive at information inputs 46 and 47 of the ALB 15. When implementing the ALB 15 arithmetic function AB, when the code of the number from register 13 is greater than or equal to the code of the number from register 14, the information outputs of the ALB 15, the difference of codes is highlighted, and at its output- Transfer - the log level. 1. Level- log. 1 from the output The transfer enters the D input of the trigger lOj, to the C input of which a pulse arrives from the single-oscillator 8. Under the action of this pulse, the trigger 10 is set to one state and allows the pulse to pass from the single-vibrator 9 through the elements AND 17 and OR 19 to upi-lui jc i / ii. j net Equalizing input of register 16 and P-input

0

trigger 26. In this case, the result is copied from the information outputs of APS 15 to register 16 and trigger 26 on the control inputs of the ALB 15, confirms its execution of function AB.

When ALB 15 implements an arithmetic function A – B, when the code of the number from register 13 is less than the code of the number from register 14, the information output of the ALB 13 shows the difference of codes in the additional code, and at its output Transfer is the level of the log. A. At the same time, under the action of a pulse from a single-vibrator 8, the trigger 10 is set to the zero state and ensures the passage of TI1 pulses through an AND 18 element to the input of the divider 20 and to the shift inputs of registers 13 and 14. The decoder 21 is distributed once and twice. pulses n and 2n at their outputs, where n is the number of pulses equal to the number of register bits 13 and 14. At the time 0 is reached

five

The nth pulse at the first output of the decoder 21, the codes in registers 13 and 14 are shifted and interchanged, the nth pulse from the first output of the decoder 21 through the OR element 19 is fed to the control input of the register 16 and the R input of the trigger 26, rewriting the result from the information outputs of the ALB 15 to the register 16, confirming the status of the trigger 26, which provides the arithmetic function AB on the control inputs of the ALB 15. Upon reaching the number of pulses

at the entrance of the divider 20, equal to 2P ,. The switches are connected to the first soda inputs on registers 13 and 14, returning to the initial state, and the pulse corresponding to the thin 2p, from the second output of the decoder 21, sets the trigger 10 to the single state on the input. When ALB 15 implements an arithmetic function AB, which corresponds only to a change in the direction of movement of the measuring signal relative to the reference, trigger 22 switches with the arrival of a pulse from the pulse output of frequency divider 6. One-way vibrators 23 and 24 form a plots at their outputs pulses: one when the input signal changes from log.O to log. H, and the other - with the log. 1 on the log. O, which, via the OR element 25, set the trigger 26 to a single state on the third input, providing the ALB 15 with the implementation of function AB.

The arithmetic operation A-B is executed by ALB 15 in the same way as the arithmetic function A-B, regardless of the state of the signal log. About or log. 1 at its output Transfer, since A + B B + A.

The maximum angular rate of phase change in the transducer is defined as the maximum allowable change in the phase of the measurement signal, equal to Tf / 2 during the T-2 time of the reference signal.

Claims (1)

The proposed converter can be widely used to control and regulate in NC phase systems, for example, to control control programs recorded on a magnetic tape for matching the data of post-processor accelerations and data on acceleration coordinates on CNC machines. Invention Formula Phase shift converter for speed and acceleration code containing trans 20 25 thirty 35 40 45 50 55 responsibly the first, second and third elements And whose outputs are connected to the inputs of the first, second and third frequency dividers, respectively, the pulse generator, the first clock generator, one output of which is connected, n to the second inputs of the first synchronizer, the second and third elements And and the other output is connected to the second inputs of the first element AND, the second and third synchronizers, the outputs of the second and third elements AND are connected to the inputs of the adder, one output of which is via the fourth frequency divider and the other Directly connected to the inputs of the first element OR, the outputs of the first element AND and OR are connected respectively to the first and second information inputs of the pulse counter, the output group of which is connected to the information inputs of the first register, the output of the first frequency divider is connected to the input of the fifth frequency divider, the first one-shot, the output of which is connected to the input of the second one-oscillator, the sixth frequency divider, which is characterized by the fact that, in order to expand the field of application of the converter, the second and third Third registers, arithmetic unit, third, fourth and fifth one-shot, fourth, fifth and sixth triggers, fourth and fifth elements AND, second and third elements OR, decoder and second driver of clock pulses, the output of the first one-oscillator is connected to the input second shaper. clock pulses, the first and second outputs of which are connected to the first control inputs of the first and second registers, respectively, the output of the second the second pulse shaper, whose input is connected to the reference signal bus, the second and third pulse shapers, the inputs of which are connected to the measuring signal bus, the outputs of the first, second and third pulse shapers are connected to the first inputs of the first, second and third triggers, respectively, the outputs of which are connected to the first inputs of the first, second and third synchronizers, respectively, the outputs of the first, second and third synchronization five 0 five 0 five 0 five responsibly the first, second and third elements And whose outputs are connected to the inputs of the first, second and third frequency dividers, respectively, the pulse generator, the first clock generator, one output of which is connected, n to the second inputs of the first synchronizer, the second and third elements And and the other output is connected to the second inputs of the first element AND, the second and third synchronizers, the outputs of the second and third elements AND are connected to the inputs of the adder, one output of which is via the fourth frequency divider and the other Directly connected to the inputs of the first element OR, the outputs of the first element AND and OR are connected respectively to the first and second information inputs of the pulse counter, the output group of which is connected to the information inputs of the first register, the output of the first frequency divider is connected to the input of the fifth frequency divider, the first one-shot, the output of which is connected to the input of the second one-oscillator, the sixth frequency divider, which is characterized by the fact that, in order to expand the field of application of the converter, the second and third Third registers, arithmetic unit, third, fourth and fifth one-shot, fourth, fifth and sixth triggers, fourth and fifth elements AND, second and third elements OR, decoder and second driver of clock pulses, the output of the first one-oscillator is connected to the input second shaper. clock pulses, the first and second outputs of which are connected to the first control inputs of the first and second registers, respectively, the output of the second one-shot is connected to the setting input of the pulse counter, to the input of the third one-shot and the control input of the fourth trigger, the output of the third one-shot and the first output of the fourth trigger connected to the inputs of the fourth element And, one output of the first shaper clock pulses and the second output of the fourth trigger connected to the inputs of the fifth element And, the output of which It is connected to the input of the sixth frequency splitter and the second control inputs of the first and second registers, the outputs of the sixth frequency splitter are connected to the inputs of the decoder, the first output of which and the output of the fourth AND element are connected to the inputs of the second OR element, the output of which is connected to the control input of the third register and one input of the fifth trigger, the output of the sign bit of the pulse counter is connected to the information input of the sixth trigger, and the group of outputs of the pulse counter is connected to the information inputs of the second register Stra, outputs of the first and second registers are connected to the first and second groups of information inputs of the ALU unit, the first and second control inputs of which are connected to the first and second outputs of the fifth trigger, respectively, information outputs are connected to the information inputs of the third register, and the transfer output is connected to the information input of the fourth trigger, the second output of the fourth trigger, output the older bit of the first register is connected to the serial input of the second register, and the output of the old 5 of the second register is connected to the serial input of the first register Istra, the output of that frequency divider is connected to the control input of the sixth trigger, the outputs of which 0 through the fourth and fifth one-shot one-shot are respectively connected to the inputs of the third element OR, the output of the third element OR is connected to another input of the fifth trigger, the outputs of the first, 5 second and third frequency dividers are connected to the second inputs from the first, second and third flip-flops, the output of the pulse generator is connected to the input of the first form - 30 clock generator, IllililJIII lllllilLJJUJIilllUi Illillllllilllin .Li Editor N. Bobkova Compiled by M.Sidorova. Tehred M. Khodanych Order 6009/57 Circulation 900 Subscription VNIIGSh of the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Design, And eleven  Par.2 Proofreader M.Maksimishinets