SU1621025A1 - Computing device - Google Patents

Description

one

(21) 4606560/24

(22) 11/15/88

(46) 01.15.91. Byupo number 2

(71) Voronezh Polytechnic Institute

(72) P.Io Stepanov, A.V “Yurshin, V.I. Zakhvatov and E.M0 Vasilyev

(53) 681 „325 (088.8)

(56) Melnikov A.A., Ryzhevsky A.G., and Trifonov E.F. Processing of frequency and time pulse signals. M: Energy, 1976, p. 69, fig. 51,

In the same place, with 57, rice „45,

(54) COMPUTATIONAL DEVICE

(57) The invention relates to a high tech technique and to be used in devices that carry out multiplying-dividing operations. The purpose of the invention is to increase the functionality by dividing the second input frequency and increasing the speed. The computing device contains trigger 1, start bus 2, shift register 3, divider signal input 4, AND group 5, divisible signal input 6, multiplier code inputs 7 and a result counter 8, connected by a function., 1 Il.

The invention relates to computing and can be used in devices that produce multiplies.

Tsep.u invention is ras-. widening of functionality due to dating to the second input frequency and speeding up

devices 4

The drawing shows the functional diagram of the device

The computing device contains trigger 1, start bus 2, shift register 3, divider 4 input 4, AND 5 group of elements, divide 6 signal input 6, multiplier code inputs 7 and a result counter 8, functionally interconnected

The computing device performs multiplying-dividing operations of the form

N P I1 (1)

R2.

The device works as follows.

Before the start of execution, the operator (1) at the input 6 of the device is given a signal divisible at a frequency f4, at input 4 - a divider signal with frequency ЕЈ, at inputs 7 - position code P multiplier

P -aQ + a-2 +

000 + ar-1

PI

; -, 2 (2)

|

where a i is the value of the 1st bit of the position code. Р multiplier; P is the number of bits of the multiplier code;

one is written to the shift register 3, the result counter 8 is reset to

According to the Start signal applied to the input 2 of the device, the output of the trigger 1 is set to logical 1, which is fed to the control input of the shift register 3 and translates it from the storage mode to the information shift mode.

In accordance with the divider signal from the device input 4 to the clock input of the shift register 3, the shift register 3 starts alternately with the period t, where 1

put on its information outputs logical 1, arriving at the second inputs of the corresponding elements And 5.

Thus, at the second input of each of the And 5 elements, alternately, during the time t2, there will be a logical 1, necessary for passing pulses of the dividend signal through each of the And 5 elements.

The number 1 pulses appearing at the output of the 1st element AND 5 is determined by the expression

one;

aW f i

or

t; a, c-d f 4

(3)

Impulses I, arriving at the counting input of the 1st bit of the counter 8 of the result, will be recorded in the counter of the result

five

"

five

0

five

0

five

number N ;:

N

I - 2

i-

(four)

one

Since all the bits of the counter 8 of the result are connected in series, then at the next recording of the numbers N through the counting inputs P of the bits of the counter of the result, the number N will be written in it:

R

N XN ;-( 5)

Sequentially substituting expressions (4) and (3) into (5), we obtain

Рi -

a, -, 2 Ј "

N -tU

after which the expression (5) acquires

view

N P f1,

f2

representing the result of operation (1)

The shift register, after setting a logical 1 at the Pm information output, produces a signal at the exit of the completion of the shift cycle, which arrives at the zero input of the trigger 1 and converts it to the zero state, thereby stopping the operation of the device

The execution time of operation (1) is determined by the expression

T K t

2

where K is the number of bits required to represent the number P, K P;

or

K f "

Claims (1)

Invention Formula A computing device containing a group of elements AND and a result counter, the first inputs of elements AND of a group are connected respectively to the positional bits of the input of the device multiplier, and the outputs of elements AND are connected respectively to the inputs of the bits of the result counter, characterized in that by dividing by wto 210256 The device enters a frequency and speeds up the device, a trigger and a shift register are entered into it, the first frequency input of the device is connected to the second inputs of elements AND a register whose input is connected to the second frequency input of the device, the third inputs of the elements I are connected respectively to the bit outputs of the shift register, the output of the shift end of which is connected to the input om setup in o trigger ten 15