SU974594A1 - Reversible pulse counter - Google Patents

Description

(5) REVERSIBLE PULSE COUNTER

The invention of oTHOcViTCfl to pulse technology and can be used in automation devices, computing and measuring equipment. j A reversible pulse counter is known that contains series-connected reversible counting bits, matching elements and triggers 1.

Also known is a reversible pulse counter containing sequentially connected reversible countable bits, the addition and subtraction inputs of the first of which are connected to the outputs of the first and second coincidence elements, the first inputs of which are interconnected, and the second inputs are connected to the first inputs of the third and fourth matches, respectively , the second inputs of which are interconnected L2,

These meters are not sufficiently functional.

The purpose of the invention is the expansion of functional capabilities.

The goal is achieved by the fact that in the device containing successively connected reversible counting bits, the addition and subtraction inputs of the first of which are connected to the outputs of the first and second coincidence elements, the first inputs of which are interconnected, 3 second inputs are connected to the first inputs of the third and the fourth elements of the match, the second inputs of the chromium volumes; are united among themselves; the first, second, third, and fourth triggers and the source of synchronization signals are introduced, the first output of which is g is very close to the first input of the first match element, and the second output to the second input of the third match element and to

Claims (2)

The 20 clock inputs of the third and fourth triggers, the direct outputs of which are connected respectively to the first inputs of the third and fourth elements of coincidence, the outputs of which are connected to the reset inputs of the first and second triggers, respectively, the direct outputs of which are connected to the information inputs of the third and fourth triggers, respectively, inverse the outputs of which are connected to the third inputs of the second and first coincidence elements, respectively, the clock inputs of the first and second triggers being inputs of devices -keeping. , FIG. 1 shows a functional diagram of the device; in fig. 2 - timing charts characterizing his work. The reversible pulse counter (Fig. 1) contains sequentially connected reversible counter bits 1, a source of 2 synchronization signals, four D-flip-flops 3-6, g ryvyr second, third and fourth elements 7-10 matches. The inputs of the adding signals 11 and subtracting 12 are connected to the clock inputs of the D-flip-flops 3, 4, respectively, the outputs of the D-flip-flops 3 t are connected to the D-inputs of the O-flip flops 5 and 6, respectively, the clock inputs of the 0-flip-flops 5 and 6 are connected to the first output of the source 2 of the synchronization signals, the direct outputs of the D triggers 5 and 6 are connected to the first inputs of the third 7 and fourth 8 coincidence elements, respectively, the second inputs of which are connected to the second output of the source 2 synchronization signals, the outputs of the elements 7, B coincidence are connected to entrance The reset of O-flip-flops 3 and 4, respectively, the inverse outputs 0-flip-flop 8 5 and 6 are connected to the inputs of elements 10, 9 of the co-fall, respectively, the second inputs of which are connected to the direct outputs of flip-flops 6 and 5, respectively, and the third inputs of elements 9 the source output is connected to nick 2 synchronization signals, the outputs of elements 9 S coincidence are connected to the addition and subtraction inputs of the first counting decade 1, respectively. Information inputs 13 and 14 of the trigger 3 and 4 are connected to the potential potential unit bus. The device works as follows. In the initial position (Fig. 2d, e, K, A), the triggers 3-6 are in the zero state. At the outputs of the elements of coincidence 7-10, the level of the logical unit (Fig. 2i, i, 0, p). Counting signals. arriving simultaneously (in the same interval between adjacent pulses T.-a) through the addition tires (Fig. 2) and subtraction (Fig. 22), triggers 3 and A are switched to a single state (Fig. 2.1c). The nearest pulse T from the second output of the source of the synchronizing signals (Fig. 2d) sets the triggers 5 and 6 into one state (Fig. 2e, d), the same clock pulse through the elements 7, 8 coincidence (Fig. 2i, n) sets triggers 3 and to zero (initial) state. At the outputs of elements 9, Yu coincidence continues / remains the levels of the logical unit, since their first inputs from the inverse outputs of the flip-flops 5 and 6 (Fig. 2g, / l) receive the levels of logical zero. The following clock pulse (Fig. 2c) returns the triggers 5 and 6 to the zero (initial) state. Thus, with simultaneous input of signals on the addition and subtraction buses or their arrival with a shift, but in the same interval between two adjacent clock pulses, the pulses do not arrive at the input of the counting decade. Upon receipt of the next pair of pulses on the addition and subtraction tires (Fig. 2, g, when the clock pulse T ;, is located between them, each channel of the counter operates as indicated, but with a shift determined by the intervals between the counters.) If an early impulse arrives through the bus addition, then (at the first and second inputs of element 9, the logic unit levels) the pulse from the first output of the signal synchronization source (Fig. 2ff) is fed to the input of the addition of countable bit 1. At this time, at the output of element 10, the level of logical units Since the pulse arrives on the subtraction bus, when the first and second inputs of the element 10 match the level of the logical unit, the pulse from the first output of the clock source is fed to the subtraction input of the counter bit. this is the time at the output of element 9 the level of a logical unit, since at its first and second inputs there are levels of logical zero, Thus, the introduction of additional elements - triggers into the counter, the source of the synchronizing signal in 59 it provides the possibility of counting signals with an arbitrary location in time, while signals arriving simultaneously on both channels are blocked with the help of special keys. In the case of signals arriving at different times, the counting pulses at the input of the counting bits are generated synchronously with the same auxiliary sequence of pulses. This expands the functionality of the device by providing a combined counting of input signals randomly arranged in time. Claims of the invention A reversible pulse counter containing successively connected reversible countable bits, the addition and subtraction inputs of the first of which are connected to the outputs of the first and second coincidence elements, the first inputs of which are interconnected, and the second inputs are connected to the first inputs of the third and fourth matches, respectively whose second inputs are interconnected, NO 1 I / If If t characterized by the fact that, in order to expand its functionality, the first, second, third and fourth triggers and the source of synchronization signals are introduced into it, the first output of which is connected to the first input of the first match element, and the second output is KQ to the second the input of the third match element and the clock inputs of the third and fourth triggers, the forward outputs of which are connected respectively to the first inputs of the third and fourth match elements, the outputs of which are connected to the reset inputs of the first first and second flip-flops, straight outputs of which are connected to the data inputs of the third and fourth flip-flops, inverted outputs of which are connected stretimi inputs respectively the second and first overlaps, said clock inputs of said first and second flip-flops are inputs. Sources of information taken into account during the examination 1. USSR author's certificate No. 550767, cl. H 03 K 23/00, 1976. 2. USSR author's certificate number SItSB, cl. H 03 K 23/00, 1970 (prototype). P. Jt /but l l l fd P. b g and Tl at well and and to P l m If n o p l l l l l l l and fg f ig