SU824447A1 - Frequency divider - Google Patents

Description

(54) FREQUENCY DIVER

one

Vibration refers to pa otohex / nick and can be used in devices for dividing the frequency and forming clock grids in automation and computer systems.

A device is known that contains two scaling circuits, each of which consists of a decoder with a counter connected to it with one counting input and a zero state setting input, two gates with two separate inputs and one output that is connected to one of the inputs of the TID element, and trigger with a counting input, the input of the installation and the left state of one of the meters is connected to the counting input of another counter, the installation input is zero, the state of which is connected to the counting input of the trigger, with one of the same name nye vhsady valves combined with each other and connected to the trigger outputs and inputs of the same name Druts gates connected to the outputs of its counting circuits of the decoder.

The disadvantages of the known device is the complexity and, in addition, the output signal of this device has a duty cycle different from two,

It is also known a frequency division device comprising a pulse generator, two triggers and four NAND elements, pulse distributor, I / O. the house is connected to the pulse generator, and the outputs are the K-first inputs of the four AND-NOT elements and the comparison element, the second input of the first AND-NE element is connected to the zero output of the BTOjioro trigger, and the output to the single input of the first trigger, the output of the second AND element NOT connected to the zero input of the first trigger, and the second input to the unit output of the second trigger and to the input of the comparison element, the other input of which is connected to the unit output of the first trigger and to the second input of the third element AND-HHO, output of the third element And NAND is connected to the single input of the second trigger, the zero output of the first trigger is connected to the second input of the fourth NAND element, the output of which is connected to the zero input of the second trigger. The known divider provides a duty cycle of the output signal equal to two 2.

Claims (2)

A disadvantage of this device is the G-limit functionality, i.e. it does not provide a division factor other than 1.5. The purpose of the invention is the extension of functional capabilities, and it is precisely the provision of division by N + 0.5, where G is a whole, odd (even) number. . The goal is achieved by the fact that in a frequency divider containing a pulse generator connected to a pulse distributor whose outputs are connected to the first inputs of four corresponding AND-NOT elements, the outputs of the first and second AND-NOT elements are connected respectively to the single and zero inputs of the first the trigger, and the outputs of the third and fourth elements AND-NOT to the single and zero inputs of the second trigger, the output of the first trigger is connected to the input of the comparison element, the other input of which is connected to the output of the second K-bit shift registers are entered where N + 1, H f, l-t and the input of the first register is connected to the output of the first trigger, and the register input is from the quarter (first) output of the pulse distributor, its single output is with the second input of the third element AND-N and zero output with the second input of the fourth element IS-NOT, the input of the second register is connected to the output of the second trigger, its clock input with the first (second) output of the pulse distributor, zero output with the second input of the first -I element and NOT a single output is a register - the second input of the second element of Fig. Figure 1 shows the electrical frequency divider circuit by N + 0.5, where N .3 is an odd number; in fig. 2 is a timing diagram of the operation of the divider shown in FIG. one; in fig. 3 - electrical frequency divider circuit by N + 0.5, where N 2 is an even number; in fig. 4 is a timing diagram of the divider shown in FIG. 3. The pulse generator 1 is connected to the pulse distributor 2, the outputs of which are connected, respectively, to the first inputs of the NANDI elements 3 - b, the fourth and the first outputs of the distributor 2 pulses are also connected to the clock inputs of the shift registers 7 and 8. Zero and single outputs c / zvigovogo register 8 are connected concurrently to the second vrkhdam, elements AND-NOT 3 and 4 .. The outputs of the elements AND-NOT 3 and 4 are connected respectively to the single and zero inputs of the trigger, 9, the output of which is connected to the input of the register 7 and first of all at entry element 10 comparison. The single and zero P1XDDs of the shift register 7 are connected respectively to the second inputs of the Y-NOT 5 and 6 elements. The outputs of the AND-NE 5 and b elements are respectively connected to the single I zero inputs of the trigger 11. The output of the trigger 11 is connected to the second input of the comparison element 10 and The shift register register 8. The divider operation shown in FIG. 1, is accompanied by a timing diagram, where :; , - the signal at the output of the pulse generator 1; ,,, - signals at the outputs of the distributor 2 pulses; - signal at the single input of the trigger 9; - signal at the zero input of the trigger 9; - the signal at the output of the trigger 9; - the signal at the output of the shift register 7; - signal single input trigger 11; - the signal at the zero input of the trigger 11; - the signal at the output of the trigger 11; - the signal at the output of the shift register 8; - signal at the output of the reference element 10. The pulse generator 1 is connected to the pulse distributor 2, the outputs of which are connected respectively to the first inputs of the NAND units 3-6, with the first and second outputs of the distributor 2 pulses also connected to the clock inputs of the shift registers 7 and 8. Zero and single outputs of the shift register 8 connected respectively to the second inputs of the elements AND-NOT 3 and 4. The outputs of the elements AND-NOT 3 and 4 are connected respectively to the single and zero inputs of the trigger 9, the output of which is connected to the input of the register 7 and to the first input element 10 comparison. Single and zero outputs of the shift register 7 are connected respectively to the second inputs of the elements AND-NOT 5 and b. The outputs of the AND-NE elements 5 and b are connected respectively to the unit and zero inputs of the trigger 11. The output of the trigger 11 is connected to the second input of the comparison element 10 and to the input of the shift register 8. The divider operation shown in FIG. 3 is accompanied by a time diagram, where : and "2 is the signal at the output of the pulse generator 1; ,, D02 - signals at the outputs of the distributor 2 pulses .; - a sign on the single input of the trigger 9; - signal at the zero input of the trigger 9; - the signal at the trigger output - the signal at the output of the shift register 7; - the signal at the unit input of the trigger 11; - the signal at the zero input of the trigger 11; - signal on trigger output 11; - the output signal shift register 8; - the signal at the output of the element 10 compared. The device (Fig. 1, Fig. 2) operates as follows. The signal at the output of the shift register 8 is in the zero state. Then the zero output of this register opens the element IS-NE 3 and when the first clock arrives from the distributor 2 pulses (pulse generator 1 and pulse distributor 2 serve to generate signals ... shifted by 1/5 period of the input frequency) at the output This circuit produces a negative polarity signal, which translates trigger 9 from zero to one. Since N + 1 is a negative state. j -----, then at a single output of the shift register 7, the signal is generated through two clock pulses after its appearance on the RS flip-flop 9. This signal opens the element AND-HE 5 and when the fourth clock pulse from the distributor 2 pulses at the element output AND-NOT 5 is generated by a negative polarity sgNSh, which translates trigger 11 from a zero to one state. A single output of the shift register 8 generates a signal through two shift cycles. A single output of this register opens an AND-NOT 4 element and when it arrives at the output, a negative polarity signal is generated, which translates trigger 9 from one to zero, after which the shift register 7 changes from one to zero in two shear stroke The zero output of this register opens the NAND element, and when the shear cycle arrives at the output, a negative polarity signal is produced which translates the trigger 11 from one to the zero state, and the whole cycle repeats again. Thus, the outputs of flip-flops 9 and 11 produce signals equal to seven periods of the input frequency and shifted relative to each other by 1/4 of the period. Comparison element 10 multiplies this frequency by two, and thus, the output produces a signal whose period is equal to 3 and 5 periods of the input frequency. The device shown in FIG. 3, works in a similar way. The invention The frequency divider containing a pulse generator connected to a pulse distributor, the outputs of which are connected to the first inputs of the four corresponding elements AND-NOT, the outputs of the first and second elements AND-NOT are connected respectively to the single and zero inputs of the first trigger, and the outputs of the third and fourth NAND elements - to the single and zero inputs, the second trigger, the output of the first trigger is connected to the input of the comparison element, the other input of which is connected to the output of the second trigger, o t It is also due to the fact that, in order to expand the functionality, namely, to ensure division by N + 0.5, where N is an odd (even) integer, two K-bit shift registers are entered into it, where K -ii- (), with the input of the first register connected to the output of the first-. first trigger, the clock input of the register is with the fourth (first) output of the pulse distributor, its single output is with the second input of the third AND-NOT element, and the zero output is with the second input of the fourth AND-NOT element, the second register input is connected to the output of the second trigger , its clocking input - with the first (second) output of the distributor, pulses, zero output with the second input of the first NAND element, the unit output of this register - with the second input of the second NAND element. Sources of information taken into account in the examination 1. USSR author's certificate 437229, cl. H 03 K 23/02, 1972. 2. USSR author's certificate in application 2774612, cl. H 03 K 23/02, 14.06.79. WITH MP V-4 / with eight . eleven 6 I 0-1 .JT WITH 9 7 | -A d 7 fs // " i-g one J L Fia.