SU1287281A1 - Frequency divider with fractional countdown - Google Patents

Abstract

The invention relates to a pulse technique and can be used in frequency grid drivers and other frequency conversion devices. The purpose of the invention is to expand the functionality achieved by providing the coefficient of the division factor by N + -. Where N, K and M are integers. For this purpose, a ring register 5 and a pulse distributor 6 are entered into the divider. In addition, the divider contains counter 1, decoder 2, output bus 3, element M-2I-ShSh 4, input bus 7, Compared to the prototype, the frequency divider has wider functionality, since it allows one to obtain a smaller and arbitrary step of changing the division factor. 5 il.

Description

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The device relates to a pulse technique and can be used in frequency grid drivers and other frequency conversion devices.

The aim of the invention is to enhance the functionality by changing the division ratio. In this case, the division ratio may

To be specified in the form of N + TG, where N, K,

M - any integers.

FIG. 1 shows a block diagram of a frequency divider with a fractional division factor} in FIG. 2 shows examples of specific embodiments of the device for certain division factors; FIG. 3 - 5 - pulse diagrams of the device operation.

The frequency divider with a fractional division factor contains an integer divisor consisting of counter 1 with decoder 2 connected to its output, the output of which is the output of divider by integer and connected to the output bus 3 of the device and the installation input of counter 1, the element M- 2I-OR 4, the output of which is connected to the input of the counter 1, the ring register 5 and the distribution (6 pulses, the input of which is connected to the input bus 7 of the device, and the first OUTPUT - to the first input of the first element I of the element 4, the second inputs of all items and email Menta 4 is connected to the corresponding outputs of the ring register 5, the synchronization input of which is connected to the input bus 3 of the device, and the installation input to the bus 8 to reset the device to its initial state, the first input of each element And, except for the first element And element 4, is connected with the corresponding output of the distributor 6, the number of which is determined by the formula

n 2 .. M 1 + JK - iM,

where j 1 ... (M - 1) is a successively increasing coefficient by 1;

 with JK M,

i 1,2 ... with

Similarly, the division ratio by 2 2/4 can be

1 takes the values at which

the following requirement must be fulfilled 55 (figs. 26 and 4),

In: JK - 1M M. To get a 2 3/4 ratio

FIG. 3-5 denotes: a - input pulses. On bus 8; bd - they need a shift of 3/4 period, i.e. in the first cycle, output 1 is used, in the second - output 4, then output

pulses at the outputs of the distributor 6;

e, g - pulses at the outputs of counter 1; 3 - pulses at the output of the decoder 2; m-m - pulses at the outputs of the register 5} n - pulses at the output of the element 4.

The device works as follows.

In the initial state, the distributor 6 and the counter 1 can be in an arbitrary position. By an impulse on bus 8, the first bit of register 5 is set to state 1, and the rest to state O. Suppose that the bits of the counter are in the zero state.

The pulses from the first output of the distributor 6 through element 4 are fed to the input of the count 1. After the arrival of a predetermined number of pulses, the decoder 2 is triggered and the first pulse appears at the output 3 of the device. The same pulse arrives at the input of register 5, state 1 moves to the next bit, and the counter 1 receives the pulses already shifted in time from the other output of the distributor 6.

To implement the division by N + K

+ -, where N, K, M are integers, the division factor in the divisor by an integer (counter T is a decoder 2) is N + 1. The value of M is the number of outputs of the distributor 6 and

There are 35 2I elements in element 4. The number K determines the shift of the pulse sequence at the input of counter 1 after each completion of the: division division.

40

For example, to obtain a division ratio of 2 1/4 (Fig. 2a), a shift of 1/4 of the period is necessary, for which the number of outputs of the distributor

45 is chosen equal to 4, and the value of K - unit. This means that upon completion of the division cycle, it is necessary to go to the output of the pulse distributor with the number greater than 1, i.e.

50 in the first cycle, the signal comes from the first output, in the second - from the second, in the third - from the third, etc.

Similarly, the division ratio by 2 2/4 can be organized.

a shift of 3/4 of the period is necessary, i.e., output 1 is used in the first cycle, output 4 in the second, then output

3 (4-1-2-3), then 2 (3-4-1-2) and then again output 1 (2-3-4-1).

The selection of the values of K and M in general form can be made as described in the claims.

Compared with the device-prototype, the frequency divider according to the invention has broader functionality, since allows you to get a smaller and arbitrary step change in the division factor.

K, M are integers, a ring register and a pulse distributor are entered in it, the input of which is connected to the input bus of the device, and the first output is connected to the first input of the first element AND element M-2И-Ш1И, the second input of the first and the first inputs of all other elements Element M-2I-Ш1 is connected to the corresponding outputs of the ring register in increasing direction, the synchronization input of which is connected to the output bus of the device, and the installation input is connected to the bus of installation of the device into the initial

Claims (2)

Claims of the invention, 5 states shGe, with the second input of each element AND A fractional splitter frequency divider containing an integer divisor consisting of a counter with a decoder connected to its output, the output of which is the divider output of an integer and connected to the output bus of the device and the installation input of the counter, M-2I-OR element , the output of which is connected to the counting input of the counter, which is characterized by the fact that, in order to expand the functionality by providing a coefficient AND element M-2I-OR, is connected to the corresponding output of the pulse distributor, but whose measures are defined by the formula P 2 ... M 1 + JK - iM, where j 1 ...) M-1) is successively increasing — by 1;  with JK M i 1,2 ... with JK M, while 1 takes on values at which the condition division rate by N + - TO M where N, K, M are integers, a ring register and a pulse distributor are entered in it, the input of which is connected to the input bus of the device, and the first output is connected to the first input of the first element AND element M-2И-Ш1И, the second input of the first and the first inputs of all other elements Element M-2I-Sh1I is connected to the corresponding outputs of the ring register in increasing direction, the synchronization input of which is connected to the output bus of the device, and the installation input to the device installation bus the second step, with the second entrance every 25 element And element M-2I-OR is connected to the corresponding output of the pulse distributor, the number of which is determined by the formula n 2 ... M 1 + JK - iM, where j 1 ...) M-1) is successively increasing — by 1;  with JK M i 1,2 ... with JK M, while 1 takes on values at which the condition  JK - iM: $: M. PU8. J