SU742913A1 - Timing pulse shaper - Google Patents

Description

The invention relates to automation and computing and can be used in discrete automatics systems and control devices of specialized computers to form a series of clock pulses. A known clock pulse former contains a counter, a decrypted oscillator, a control unit, and AND elements C13. However, the known driver does not provide the output of a series of clock pulses with a predetermined number of pulses in each series, as well as individual pulse series. In addition, it does not ensure the formation of sequences with a variable number of pulses consisting of any like clock pulses that follow frequency of the master gene generator The closest in technical terms to the invention is a clock generator, comprising a master oscillator, a control unit, a counter, a cycle counter, a decoder, a delay element, the first and second IC2 elements. The disadvantages of the well-known driver are not ensuring the issuance of series of clock pulses with a variable number of batches, the formation of sequences of clock series with a variable number of pulses consisting of any combination of clock pulses, and the formation of sequences with a variable number of pulses consisting of any clock pulses that follow the frequency of the master oscillator. The purpose of the invention is to expand the functionality, namely the formation of a series with an arbitrary number and numbers of clock pulses in the series. The goal is achieved by the fact that the driver of clock pulses, which contains the master oscillator, has a block of

control, counter, cycle counter, decoder, delay element, first and second elements AND, the first output of the control unit being connected to the first Vcoau of the first element AND whose output ™ Go is connected to the installation input from; a picker whose output is connected to the input of the unit control, the output of the master oscillator is connected to the first input of the second element I, the output of which is connected to the counter of the counter, the installation input of which is connected to the output of the delay element, and the output to the first input of the decoder, the outputs of which The outputs of the TaATijfVfcsx pulse generator, the control decoder, the register of the feature, the first and second triggers, the OR element, and the second output of the control unit are connected to the input of the characteristic register, the output of which is connected to the second input of the first element AND and to the control input the control decoder whose inputs are connected to the decoder pins, the first output to the tiepOMy input of the OR element, the second output to the counting input of the cycle counter, the third output to the single input of the trans. Vogo triggers, zero inputs of the first and second triggers and the second input of the OR element are connected to the output of the box counter, the single input of the second trigger to the first output of the control unit, zero output of the first and single output of the second trigger are connected respectively to the second and third inputs of the second element AND , the output of the master oscillator through the element is NOT connected to the second input of the decoder, the output of the element OR to the input of the delay element.

The drawing shows a functional diagram of the shaper.

The clock pulse generator contains a control block 1, a register 2 of a sign, a counter 3, a counter of 4 cycles, a master oscillator 5, a decoder 6, a control decoder 7, the first second second triggers 8 and 9, the element 1О И / 1И, the first and ВТО1.1ОЙ elements 11 and 12 AND, element 13 is NOT, element 14 is delay and outputs 15,. about . , 15 shaper.

Shaper clock pulses works as follows.

Before you start, the register 2 features, the counter 4 cycles, the first trigger 8, the second trigger 9 and the counter

3 is set to the zero (initial) state (the installation circuit of the memory elements is not shown in the drawing).

6, the sequence of forming a series of clock pulses, operation, begins with an entry in register 2 of the control word flag. The control word is generated at the second output of the control unit 1 and determines the operation mode of the formatter.

After the control word is written to register 2, the control unit 1

generates a nerve signal Start. This signal triggers the first element 11 And the counter of 4 cycles records the number equal to the number of series of clock pulses, which

rye need to form. At the same time, the Start signal sets the second trigger 9 to one state. The signal from the single output of the second trigger 9 goes to the third input of the second element 12 I, the second input of which is supplied with an enable signal from the zero output of the first trigger 8. Thereafter, the clock pulses from the output of the master oscillator 5 through open

the second element 12 And begin to arrive at the counting input of the counter 3. At the moment of the absence of a clock pulse, the signal that the polling of the decoder 6 does NOT appear at the output of the element 13

Depending on the state of the counters 3, the decoder 6 forms a series of clock pulses, which are successively fed to the output buses 15,. . ., i5 and to the inputs of the control descramble

7. The information inputs in the form of a parallel code from the output of register 2 of the characteristic are supplied to the control inputs of the control de- fector 7. In this mode, from the output of register 2, the sign comes

This is the code with which the control of the SOFTWARE decoder 7 is prepared to operate at the moment of the formation of the last clock pulse in the series. According to the signal from the second control output

the decoder 7, the counter 4 Tsishov records the fact that the first series of clock pulses was issued. The signal from the first output of the control decoder 7 through the element 10 OR and the delay element 14

em to the installation input of the counter 3, its transfer to the initial (zero) state. After that, the clock pulse shaper begins to generate the next series of clock pulses, which is formed similarly to the above described. After the necessary number of clock pulses has been formed, a signal is generated at the output of the counter for 4 cycles, which goes to the zero inputs of the first and second triggers 8 and 9 and to the installation input of the counter 3, set them to the initial (zero) state. This concludes the process of forming a series of clock pulses. At the same time, the signal from the output of the 4-cycle counter enters the control unit 1, which updates the contents of register 2 of the flag. According to the next Start signal, the driver generates a new sequence with a specified number of clock series. In the mode of forming sequences of a series of clock pulses with a variable number of pulses consisting of any combination of clock pulses, the operation of the driver also begins with writing to the register 2 a sign of the control word. In this mode, the control word contains the number of clock series, the number of clock pulses in the series and the number of the last clock pulse in the series. On a signal, the Start from register 2 of the feature through the element 11 And the 4-cycle counter records the number / V, which is calculated using the formula / V (f +, where iyy is the number of series of clock pulses in the sequence a / t - the number of operations required , switching on the used clock pulses from the complete series. Simultaneously the Start signal sets the trigger to one state 6. The process of forming a series of clock pulses begins. If it is necessary to exclude the corresponding clock pulse from the series, then based on the information from the register 2 n output From the output of the decoder 6, the control decoder 7 is triggered from the output of the decoder 6. In this case, the control decoder 7 generates signals on the first and second outputs. The signal from the first output of the control decoder 7 switches the counter 3 to the state corresponding to the formation of the next impulse of the series clock pulses. The signal from the second output goes to the counting input of the counter 4 cycles, where the fact of the execution of the exclusion operation H9 using 36 smyh clock pulses from the full series is recorded. An alternate signal from the output of the f-lE element 13 generates another clock pulse. After the last clock pulse has been outputted, the first and second outputs of the control decoder 7 generate the signals of the signal. The signal from the first output of the decoder 7 sets the counter 3 to the initial (zero) state, and the signal from the second output goes to the counting input of the 4-cycle counter, which records the fact of the issuance of the first series of clock pulses consisting of the selected combination of clock pulses. After the required number of clock pulses has been formed, the 4-cycle counter generates a control signal that sets the first and second triggers 8 and 9; counter 3 to the initial (zero) state. In the mode of forming sequences with a variable number of pulses consisting of any b-like clock pulses following the frequency of the master oscillator 5, the control word contains information about the number of clock pulses D of the sequence to the number of the clock pulse. After the control word is written to the register 2 of the characteristic, the control unit 1 generates a Start signal, by which a number equal to the number of clock pulses of the same name in the sequence to be generated is recorded in the 4-cycle counter. At the same time on the Start signal, the decoder 6 begins to generate clock pulses, which are fed to the outputs of the 15 is driver. When the clock pulse is formed at the output of the decoder 6, the number of which is recorded in the register 2 of the feature and which needs to be developed with the frequency of the master oscillator 5, the decoder 7 is activated. In this case, the decoder 7 generates control signals only at the second and third inputs. The signal from the second output of the decoder 7 is fed to the counting input of the counter of 4 cycles, where the fact of the first clock pulse generated by the sequence is recorded. The signal from the reethe output of the decoder 7 sets the first rigger 8 to one state. As a result, it removes the enable signal that arrives at the second input of the second element 12 I and further input stops.

7

pulses from the output of an ecumenately geyiratora 5 to the counting input of counter 3. Counter 3 retains its state corresponding to the formation of the required clock pulse. According to the signals from the output of the element 13 NOT, i.e., with the frequency of the master oscillator 5, at the corresponding course .15, .., 15, is formed after. timing of pulses.

At the rate of issuance of pulses

decoder 7 (| signal to the second and third outputs. On the signal from the second output of the decoder 7, counter 4 counts the number of generated clock pulses. After the sequence of the required number of clock pulses has been formed, the counter 4 cycles generates controls, sets the triggers 8 and 9 and the ZB counter to the initial (zero) state. At this process of forming a sequence consisting of the same time clock pulsed clock signals, which, from the frequency of the master oscillator, finish At the same time, using the signal from the output CHSTHViKa 4, the control unit 1 can write to the register 2 of the sign of the new information, setting, thereby, one of the operating modes of the clock pulse generator.

The economic effect from the use of the invention lies in the fact that the clock pulse generator provides for the issuance of a series of clock pulses with a variable number of batches, the formation of sequences of clock pulses with a variable number of pulses, as well as the formation of a sequence, of irregularities with a variable number of imgg / lsov, state (the CEC of any one-time tact. Uk gp-l.pulsov that follow with the frequency of the master oscillator

Formula and 3 optics

Clock driver, containing master oscillator, block

13c

control, counter, meter count, switch, delay element, first and second elements AND, the first output of the control unit connected to the first input of the first element AND whose output is connected to the installation input

CALCULATION cycles, the output of which is to the input of the control unit, the output of the master oscillator is connected to the first input of the second element I, the output of which is connected to the counting input of the counter, the setup input of which is connected to the output of the delay element, and the output to the first input of the decoder, the outputs of which are outputs of a clock pulse generator, characterized in that, in order to extend the functionality by forming a series with an arbitrary number and numbers of clock pulses in a series, it contains control the decoder, the register of the feature, the first and second triggers, the OR element, the NO element, and the second output of the control unit is connected to the input of the register of the sign, the output of which is connected to the second input of the first AND element and to the control input of the control decoder, whose inputs are connected to decoder outputs, the first output to the first input of the OR element, the second output to the counting input of the cycle counter, the third output to the single input of the first trigger, zero inputs of the first and second triggers and the second input of the OR element are connected to the output of the counter ts1shov, a single input of the second trigger to the first output of the control unit, the zero output of the first and the unit output of the second trigger are connected respectively to the second and third inputs of the second element 1. - the output of the chrebe master oscillator is not connected to the second r: . element OR - to Vloda element zaerg th.

Sources of information, U1 i: (into account when examining

1.Avtorr: s USSR certificate

d 262490, cl. GI F F 1/04, 12.O7.68

2, ABfrjpi USSR Soyuz State

N 349997, class, Q 06 F 1/04, 08.02.71 (prototype),

Claims (1)

Formula invented by me and I A clock generator containing a master oscillator, the unit of which is connected to the counter input of the counter, the installation input of which is connected to the output of the delay element, and the output to the first input of the decoder, the outputs of which are the outputs of the clock generator, characterized in that, in order to expand the functional opportunities due to the formation of series with an arbitrary number and numbers of clock pulses in a series, it contains a control decoder, a sign register, the first and second triggers, an OR element, an ele ent NOT, moreover, the second output of the control unit is connected to the input of the attribute register, the output of which is connected to the second input of the first AND element and to the control input of the control decoder, the inputs of which are connected to the outputs of the decoder, the first output to the first input of the OR element, the second output to to the counting input of the cycle counter, the third output to the single input of the first trigger, the zero inputs of the first and second triggers and the second input of the OR element are connected to the output of the cycle counter, the single input of the second trigger to the first output of the control unit, the zero output of the first and the single output of the second triggers are connected respectively to the second and third inputs of the second element I. The output of the master oscillator through the element is NOT connected to the second input of the decoder, the output of the OR element is connected to the input of the delay element.