SU1287259A1 - Generator of quasiregular pulses - Google Patents

Abstract

The invention can be used in probabilistic modeling equipment of automation and computer technology. The purpose of the invention is to expand the functional possibilities of adjusting the statistical parameters of the generated pulse train. To do this, a delay element 5 is introduced into the device, counter 8,. shaper 9 pulses, RS-flip-flop 10 and block 11 comparison codes. The device also contains shift offset 1, a decoder 2, an adder 3 modulo two, an element OR 4, a group of elements AND 6, a generator of 7 clock pulses, an element 12 and a block 13 of control codes. When this shift register 1, the adder 3 modulo two, the decoder 2 and the element OR 4 form the M-sequence generator, forming a pseudo-random code.

Description

The invention relates to a pulse technique and can be used in probabilistic modeling equipment of automation and computing technology.

The aim of the invention is to extend the functionality by providing adjustment of the statistical parameters of the generated pulse train.

The drawing shows a block diagram of a generator of quasi-regular pulses.

The generator of quasi-regular pulses contains the shift register 1, the first group of outputs of which is connected to the inputs of the decoder 2, the adder 3 modulo two, the element OR 4, the delay element 5, the group 6 of elements And, the generator 7 clock pulses, counter 8, a pulse shaper 9, an RS flip-flop 10, a code comparison block 11, the output of which is connected to the first input of an And 12 element, a control code block 13. The output of the element 12 is connected to the first installation input of the RS flip-flop 10, the installation input of the counter 8, the input of the delay element 5 and the synchronization input of the shift register 1, the outputs of the last and J-ro bits of which are connected to the first and second inputs of the adder respectively 3 modulo two, the output of which is connected to the first input of the element OR 4, the second input of which is connected to the output of the decoder 2, and the output to the information input of the shift register 1, the outputs of the second group of output which are connected to the first inputs of the corresponding elements And 6 groups of elements And, the outputs of elements And of which are connected to the corresponding inputs of the installation of the bits of the counter 8, the outputs of the bits of which are connected to the corresponding inputs of the first group of inputs of the code comparison unit 11, the inputs of the second group of inputs of which are connected to the corresponding outputs of the control unit 13 codes. The output of the generator 7 clock pulses is connected to the counting input of the counter, the output of the last bit of which is connected to the second installation input of the RS flip-flop 10 through the pulse shaper 9, the output of which is connected to the second input of the And. 12 element. The output of the delay element 5

connected to the combined second inputs of elements And a group of 6 elements I.

The generator of quasi-regular pulses operates as follows.

The period of the quasi-regular pulses Tk is determined by three independent factors: the pulse following period at the output of the generator 7 clock pulses T ,,, the pseudo-random code K rewritable from the shift register 1 to the counter 8 by the delayed output pulse, and the Kc code value set to block 13 control codes. The change in the values of the mean time period and its variance is carried out in two stages. First, the value of period T is selected, which is related to a certain ratio with the magnitude of the variance b:

T -.

and where c is a constant;

k - register shift 1 shift; Then, the value of the Ku code is selected based on the given average value of the period of the quasi-regular pulses T according to the following formula:

TO"

H

Tk, “and

Thus, the magnitude of the variance b depends on the chosen value of Tu, and the constant (for a particular device) magnitude K, and the magnitude of Tu depends on the same (the previously chosen T, K values and the magnitude K, which does not affect the variation of the variance b .

Shift register 1, modulo-2 adder 3, decoder 2, and OR element A consist of a M-sequence generator, which forms a pseudo-random code Hz. The quasi-regular nature of the change in the pulse pulse period is due to the fact that the pseudo-random values of the K code are rewritten into counter 8, which leads to a time delay (due to counting 2 - Kz pulses) between the instances of code K census and overflow of the counter 8 by the value Tp, determined Kts value and uniformly distributed from T to 2 TC. An additional delay Td T. K is introduced by counting by the counter 8 clock pulses before comparing the number of counted pulses with the KU code set in block 13 of the control codes. Thus, the period values

TK TO + Tg 1 (2- Ku)

(

have two components: pseudo-random Td and constant Td, which allows for separate adjustment of the values of and T.

Let. After switching on the device, the RS flip-flop 10 is in zero,

to complete the transients in the shift register 1 and in the counter 8, write to the counter 8 to. Yes K, determined by the state of the 5 rows of the shift register 1 after the shift in it. Then the counter 8 counts clock pulses up to the moment of overflow, which occurs after a time interval of 10 TO T, (2 - K |). In this case, the RS-flip-flop 10 is set to one and the process proceeds as described above. If at the time of turning on the device RS-trigger 10

15

20

state (the first component of the period of quasi-regular pulses is formed is a pseudo-random time interval T), in the shift register

1 and counter 8 recorded random values of K and K codes, respectively. The counter 8 counts the pulses generated by the clock pulse generator 7. After coming

2 K, clock pulses counter 8 overflows.

According to the overflow signal of the counter 8, the pulse shaper 9 generates a pulse, which sets the RS-trigger 10 in one state. In this case, the inhibiting signal is removed from the second input

element And 12 and begins to form

the second (constant) is 30 s is T (2 + K ,,) T ", and

is in the unit state, the operation of the device begins with the formation of a constant component of the period of quasi-regular impulses. After the device generates 2 - 1 impulses, the values of the time intervals between which pseudo-random and evenly distributed

(2

Lena from

(1 + Cc) -T

before

Ku)

AND

; re-formed in series 25 quasi-regular pulses, in which

each of

2

one

T values repeat

It is delivered through 2 - I output pulses. The average value of

follow quasi-regular impulses

 .,):

period of quasiregular impulses Td ..

I

At the moment of coincidence of the Kg code recorded in the control code block .13 and the code defined by the current state of the bits of the counter 8, the code comparison unit 11 is triggered. The signal from the output of the code comparison block 11 is fed to the input of the And 12 element, the output of which another impulse of quasi-regular sequence is formed. This pulse sets the RS-trigger 10 and all bits of the counter 8 to the zero state, and also enters the synchronization input of the shift register 1 and transfers it to the next state determined by the previous state of its bits. In this case, the number written in shift register 1 is shifted by one bit towards the high bit, and the first bit is written one or zero, in

872594

to complete the transients in the shift register 1 and in the counter 8, it writes to the counter 8 a code K, which is determined by the state of the 5 bits of the shift register 1 after the axis of the shift. Then the counter 8 counts the clock pulses to the moment of overflow, which occurs after a time interval of 10 TO T. (2 - K |). Here, the RS flip-flop 10 is set to one and the process proceeds as described above. If at the time of turning on the device RS-trigger 10

five

0

is in a single state, then the operation of the device begins with the formation of a constant component of the period of quasi-regular pulses Td. After the device produces 2-1 pulses, the values of the time intervals between which are pseudo-random and uniformly distributed (2

Lena from

(1 + Cc) -T

before

Ku)

AND

; a sequence of 5 quasi-regular pulses is re-formed, in which

each of

2

one

T values are repeated after 2-1 I output pulses. The average value of the period

ow is T (2 + K ,,) Tn, and

Yes following quasi-regulatory impulses.,):

the variance of the period values is determined by the following expression ;.

.G

Claims (1)

Invention Formula The generator of quasi-regular pulses, containing the shift register, the first group of outputs of which is connected to the inputs of the descrambler, the modulo two adder, the element OR, the group of elements AND, the generator of clock pulses, the block of control codes, the purpose of extending the functionality by providing adjustment of the statistical parameters of the generated pulse sequence, the delay element, the counter, the pulse shaper, the R5 trigger, the code comparison unit, the output of which is connected to the first input of the element I, the output of the generator, are connected to the first installation depending on the signal at the output of the sum-55 RS trigger input, the installation mator 3 modulo two at the moment of shear. The same pulse from the output of the element And 12, delayed by the delay element 5 at the time C required the input of the counter, the input of the holding element and the synchronization input of the shift register, the outputs of the last and j-ro bits of which are connected the input of the counter, the input of the delay element and the synchronization input of the shift register, the outputs of the last and j-ro bits of which are connected to five the first and second inputs of the corresponding modulo-adder two, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the decoder, and the output to the information input of the shift register, the outputs of the second group of outputs of which are connected to the first inputs of the corresponding elements of the group of elements And, the outputs of the elements of which are connected to the corresponding inputs of the installation of the bits of the counter, the outputs of which are connected to the corresponding 87259 6 the inputs of the first group of inputs of the code comparison unit, the inputs of the second group of inputs of which are connected to the corresponding outputs of the control code block, the output of the clock generator is connected to the counting input of the counter, the output of the last bit of which is connected to the second setting through the pulse driver the input fe -trigger, the output of which is connected to the second input of the element And, the output of the delay element is connected to the combined second inputs of the elements of the group of elements I.