SU1345327A1 - Pulse delaying and shaping device - Google Patents

Abstract

The invention can be used in automation systems and ensures the reliability of the proposed device by simplifying it and extending the functionality by generating several delayed pulses along various output buses. To do this, the device additionally introduces the first 4 and second 5 elements OR, shift register 7, additional trigger 8 and switch 9. The device also contains a pulse generator 1, a pulse counter 2, a control trigger 3, a pulse driver 6, an input signal bus 10, reset bus 11, code setting bus 12 and output bus 13. To complete the device operation cycle; the output of the last bit, shift register 7 is connected to the S input of control trigger 3. 2 Il. with S (L

Description

The invention relates to a pulse technique and can be used in automation systems.

The aim of the invention is to increase reliability by simplifying the device and extending the functionality by allowing several delayed pulses to be generated on different output buses.

Fig. 1 shows a functional diagram of a delay and pulse generation device; FIG. 2 is a switch diagram.

The delay device and the formation of pulses contains a generator of 1 pulses, a counter of 2 pulses, control. trigger trigger 3, first 4 and second 5 elements OR, formative 6 pulses, shift register 7, additional trigger 8, switch 9, input bus 10, reset bus 11, code setting bus 12 and output bus 13.

Pulse generator 1 is connected to the synchronization input of a pulse counter 2, the resolution input of which is connected to the output of the second element OR 5, one of the inputs of which is connected to the output of the first element OR 4 and to the synchronization input of the shift register 7, and the other input to the output of the control trigger 3, one of the inputs of which is connected to the input signal bus, and the other input - to the reset bus, to the first input of the additional trigger 8 and to the zero input of the shift register 7, the n input of which is connected to the output of the additional trigger 8, the second input which is connected to the output of the first bit of the register 7 shift. Register Outputs 7. the shift is connected to the first group of inputs of the switch 9, the second group of inputs of which are connected to the buses 12 sets the codes, and the outputs of the switch 9 are connected to the D-inputs of the counter 2 pulses. The transfer output of the counter 2 through the driver-6 pulses is connected to one of the inputs of the first element OR 4, the second input of which is connected to the bus 10 of the input signal. The outputs of the shift register 7 are connected to the output buses 13 of the device.

A reversible counter operating in the subtraction mode was used as a pulse counter 2. The counter width of 2 pulses is determined by

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In the case of the formation of a single delayed pulse, the longest of the times: either the delay time of the pulse or the duration of the pulse, and in the case of the formation of n pulses on several buses by one time; either the duration of one pulse, or the delay of one pulse, i.e. the time of the greatest of the times n of the pulse durations and n delays, pulses. This is due to the fact that after the formation of each of the signals: delay or pulse duration, the pulse counter 2 is set to zero.

The delay and pulse shaping device operates as follows.

The impulse arriving via the reset bus 11 sets the shift register 7 to O, and the control trigger 3 and the additional trigger 8 to 1. From the output of the control trigger 3, signal 5 is fed through the second element OR 5 to the enable input of the counter 2 pulses. By this signal, information recorded on the D-inputs of pulse counter 2 is rewritten.

Q in the output bits of the counter. Since the signals O are generated at the outputs of the shift register 7, then the outputs of the switch 9, regardless of the code on the buses 12, specify codes, the signals O are generated. Therefore,

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A zero signal is set at the transfer output of the counter 2 pulses.

When the input pulse on the bus 10 input signal, control-g

Q triggered trigger 3 overturns and

a signal is set at its output. Oh, however, the reversible counter 2 pulses does not start counting pulses, since the input pulse through the first 4 and second 5 elements OR is fed to the counter enable input. The leading edge of the input pulse through signal 4 of the first 4 bits of the first register of the shift register 7 is recorded as signal 1, since a single signal is formed on the D-BXO de register of the shift register 7 1. The signal 1 from the output of the first bit of the shift register 7 sets the additional trigger 8 to the zero state and simultaneously arrives at the switch 9.

Thus, from the bus 12 for setting codes, the code for setting the delay of the first pulse (FIG. 2) 1 through the switch 9

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arrives at the D-inputs of the counter 2 pulses. During the duration of the input pulse, the delay code of the first pulse formed on the D inputs of the counter will overwrite the output bits of the reversible counter 2 pulses, and the signal 1 will be set at the transfer output of the counter.

At the end of the input pulse at the resolution input of the pulse counter 2, the signal O is set and the pulse counter starts to work for subtraction, i.e. the deduction code of the first pulse starts. When the preset delay time of the first pulse is reached, at the outputs of the bits of the pulse counter 2, the signals O are established, and a voltage difference from 1 to O is formed at the transfer output of the meter. By this voltage difference, the pulse shaper 6 generates a voltage pulse, the duration of which should be less. period of the clock frequency of the generator 1 pulses. On the leading edge of this pulse, the unit records from the first bit of the 7 shift register to the second bit, thereby

on the first output bus 13 fop ffppeto various output tires, in it is the front of the first, delayed pulse. In this case, a zero signal is set at the first digit of the shift register 7.

At the D-inputs of the pulse counter 2, through the switch 9, the code of the duration of the first pulse from the bus 12 sets the codes. The voltage pulse from the output of the imaging unit 6 through the first 4 and second 5 elements OR is fed to the resolution input of the 2 pulse counter and rewrites the code of the first pulse duration from the D inputs to the output bits of the counter 2 pulses, while a single signal is set at the transfer output of the counter. At the end of the voltage pulse from the output of the imaging unit 6, the pulse counter begins to write off the code of the duration of the first pulse. When a zero counter signal is installed at all bits of the counter transfer output, a voltage drop is generated from 1 to O and the pulse shaper 6 produces a voltage pulse, the leading edge of which rewrites 1 from the second bit of the shift register 7 to the third. Thereby the second time 5

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A row of the shift register forms a falling edge of the delayed pulse.

Similarly, the formation of subsequent output pulses. Thus, by setting the code values on the code setting buses 12, it is possible to form a sequence of delayed pulses of various duration at any time during an operation cycle.

Claims (1)

To complete the cycle of operation of the device, the output of the last digit of the shift register 7 must be connected to the S input of the control trigger 3 (shown in Fig. 1 by a dotted line). Invention Formula A delay and pulse shaping device comprising a pulse generator, a pulse counter, a control trigger, the first input of which is connected to the reset bus, and the second input to the input signal bus, a pulse driver and a code setting bus, characterized in that by simplifying the device and extending the functionality by making it possible to form several delayed pulses along There are two OR elements, a switch, an additional trigger and a shift register, the D-input of which is connected to the output of the additional trigger, the first input of which is connected to the reset bus, and the second to the output of the first discharge of the shift register, the zero input of which is connected to the reset bus, and the synchronization input to the output of the first element OR.i and to the first input of the second element OR, the second input of which is connected to the output of the control trigger, the output of the second element OR is connected to the enable input pulse counter, the D-inputs of which are connected to the outputs of the switch, the first group of inputs of which are connected. on the outputs of the shift register, and the second group of inputs - to the task tires codes, Moreover, the output of the counter through the pulse shaper is connected to the input of the first OR element, another input of which is connected to the input signal bus, the outputs of the shift register are connected to the output buses of the device va, and the pulse generator code is connected to the clock input of the pulse counter. To the task bus To the task bus-delay of the perforation of the first uMnii / ibca inpums 12. Editor N.Slobod nickname Compiled by A.Titov Tehred M.DhTSYKKorrektor I.Musk Order 4931/54 Circulation 900 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Phage.1