SU1238194A1 - Frequency multiplier - Google Patents

Abstract

The invention relates to radio engineering. The accuracy of frequency multiplication increases. The operation of the frequency multiplier is performed in two independent cycles. In the first cycle, an input frequency period code is generated. For this, the pulses from the generator G of the reference frequency are fed to the divider 2 frequency. The pulses from its output are fed to the summing counter (CC) 3. When the pulse is received, it is controlled by the buffer register 4, information (number N) with CC 3 corresponding to the input frequency period will be written into it. A control signal for writing to the buffer register 4 is generated during the pause between the reference frequency pulses using the input pulse generator 11, the AND 7 trigger 6, which receives the pause signal from the inverter 12, and the differentiating circuit 8. The signal for zeroing the CC 3 and setting the trigger 6 to the state O is formed from the control signal of the differentiating circuit B with the aid of the delay element 9 and the element 10. In the second cycle, the output frequency is synthesized from the frequency of the oscillator 1 using the code of the measured period. This is accomplished by a controlled frequency divider 3, to which a sequence of pulses of the generator 1 and the code N is sent from the buffer register 4. 2 Il. ate SS 00 g /. from 4

Description

The invention relates to radio engineering and may be provided in, for example, in various measuring devices, in particular in devices for measuring the speed of rotation of shafts, 5

The aim of the invention is to improve the frequency multiplication accuracy.

FIG. Figure 1 shows the structural electrical circuit of the proposed frequency multiplier loop; in fig. 2 - About the diagrams that show the operation of the device.

The frequency multiplier contains the generator 1 reference frequency, divider 2. frequency ,, summing counter 3, 5 buffer register 4, controlled frequency divider 5, trigger 6, the first element And 7, the differentiating circuit 8, the element 9 delay second element And 10, Shaper 11 input pulses 20 and an inverter 12.

The frequency multiplier works as follows.

. When the input frequency of the first pulse of the input frequency reaches 25 (Fig. 26), the shaper 11 generates an impulse (Fig. 2 e), which arrives at the input of the trigger 6 and converts it to state 1 (Fig. 2m,

. :; /:. -. zo

I. ....,.

During the next pause between the pulses of the reference frequency f (Fig. 2a), the first element And 7 outputs to the input

differentiating circuit 8 pulse (Fig. 2), since one input of the first element And 7 receives a signal

from the trigger code 6, and to the other input from the output of the inverter 12. An inverted signal is received (Fig. 2.3), corresponding to the pause of the pulse sequence of the generator 1 of the supports, - the frequency (Fig. 2a). In this case, the differentiating circuit 8 generates a control impulse that enters the buffer register 4 for recording information from summing counter 3. The same impulse through the delay element 9 with a delay of time tj (Fig. 2m) goes to one of the inputs of the second element 10. If the pause 50 between the pulses of the generator. of the reference part has not ended, then a signal is present at the other input of the second element 10, which is connected to the input of inverter 12. In this case, the second 55 And 10 element passes the control delayed by time t (Fig. 2k), which has turned the summing counter 3 and sets trigger 6 to the state O (Fig. 2e). The total duration of the control pulse and the delay time are chosen to be less than the length of the pause between the pulses of the reference frequency generator 1.

For the second impulse of the input part in the fi. 2 shows diagrams corresponding to the case when the pulse of the driver 11 did not fall to the beginning of the pause between the pulses of the reference frequency generator (fit. 2e, second pulse). In this case, the trigger 6 is transferred to state 1 and a pulse appears at the output of the first element And 7, which is fed to the input of the differentiating circuit 8. A control pulse is also generated (Fig. 2h) for recording information from summing counter 3 to the buffer register 4. The second element AND 10 of the control pulse delayed by time tj does not let through, since the pause between the pulses of the reference frequency generator has ended at the output of the inverter 12 and, accordingly, at the other input of the second element AND 10, the signal has the state O. Trigger 6 does not mouth the O state (Fig. 2, and.) therefore, with the beginning of the next pause between the pulses of the reference frequency generator, a pulse appears (Fig. 2) at the output of the first element And 7, which also passes through the differentiating circuit B and the delay element 9 on the input of the second element is AND 10. Since at the other input of the second element AND 10 the signal corresponds to state 1, the control pulse passes to its output, sets the summing counter and sets trigger 6 to the state. O (fig.

For the third pulse (fig. 2 &) of the input frequency in fig. 2 shows a diagram corresponding to the case when the pulse of the driver 11 did not fall to a pause between the pulses of the reference frequency generator (Fig. 2e). In this case, the trigger 6 is also transferred to state 1, but the pulse at the output of the first element And 7 is delayed until the pause begins, between the pulses of the reference frequency generator fj,. From the point in time corresponding to the beginning of the pause, the slave date is similar to the case considered.

3 . 1 for the first input frequency pulse i. the information from summing counter 3 is written to the buffer register; mp 4, after the delay time tj the summing counter 3 is zeroed, and trigger 6 is set to state O.

The pulses from the output of the reference frequency generator 1 are fed to the input of the frequency divider 2, the output of which is a sequence of pulses (Fig. 25), the period of which is K times the period of the pulses of the reference frequency generator (chart in Fig. 2, for ). After zeroing, the summing counter 3 starts counting pulses coming from the output of divider 2 frequencies having a frequency of "/ ... When the next control pulse arrives at the input of the buffer register 4, it records the number N of frequency pulses fo / K counted in the summing counter 3 during the period of the input frequency F ,, where N fe / KF

/

(chart in Fig. 2, dl).

The controlled frequency divider 5 begins to divide the frequency of the pulse sequence of the reference frequency generator 1 by N times. The frequency of the fast pulse sequence of the frequency multiplier is determined by the formula:

ROUTED Fp,. Thus, the operation of the frequency multiplier is performed in two independent cycles. In the first cycle, the code of the input frequency period is generated. In the second cycle, the output frequency is synthesized from the frequency of the reference frequency generator using the code measured

1944

. period In this case, the first cycle control is carried out in a pause between pulses f, and the control of the EITOPMM cycle - on the leading edge of the pulse f – g (Fig. 2d). This allows you to exclude the loss of the pulse when measuring the period of the input frequency, as well as failures when overwriting information in the buffer register.

Formula inventions

A frequency multiplier containing a series-connected reference frequency generator, a frequency divider, a summing counter, a buffer register and a frequency divider control, the counting input of which is connected to the output of the reference frequency generator, and a series-connected differentiating circuit and delay element And with the fact that, in order to improve the accuracy of frequency multiplication, a sequentially connected driver of input pulses was introduced; trigger and the first element And, the output of which is connected to the input of the differentiating circuit, and also connected in series the inverter and the second element And, which are connected between the output of the reference frequency generator and another input of the Trigger, the output of the Inverter is also connected to another input of the first element And, the output of the delay element connected to another input of the second element I, the output of which is connected to the installation input of a summing counter, and the differentiating circuit input connected to the input of the buffer register, while the input ormirovatel input pulse signal is input frequency multiplier.

Claims (1)

Claim A frequency multiplier comprising serially connected a reference frequency generator, a frequency divider, a totalizing counter, a buffer register and a controlled frequency divider, the counting input of which is connected to the output of the reference frequency generator, and a differentiating circuit and a delay element connected in series, In order to increase the accuracy of frequency multiplication, a shaper of input pulses, a trigger and the first element And, the output of which is connected differentially to the input, are introduced in series the circuit, as well as the inverter and the second AND element connected in series between the output of the reference frequency generator and another trigger input, the Inverter output is also connected to another input of the first AND element, the output of the delay element is connected to another input of the second And element, the output of which is connected with the installation input of the summing counter, and the output of the differentiating circuit is connected to the input of the buffer register record, while the input pulse shaper input is the signal input of the frequency multiplier.