SU1506504A2 - Frequency multiplier - Google Patents

Abstract

The invention relates to radio engineering and communications. The purpose of the invention is to expand the frequency range of the input signal. The frequency multiplier contains pulse driver 1, memory registers 2 and 3, delay elements 4 and 5, counters 6 and 7, frequency divider 8 with variable division factor, frequency divider 9, reference oscillator 10, code comparison block 11, controlled dividers 12 and 13 frequencies and code setting blocks (GCBs) 14 and 15. The introduction of GCBs 14 and 15 allows for the implementation of high dividing ratios of controlled dividers 12 and 13 without slowing down. This leads to an expansion of the frequency range of the input signal. 1 il.

Description

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about

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Dov, controlled frequency dividers 12 and 13, and code setting blocks (CBS) 14 and 15. The introduction of the BZK 14 and 15 allows for high coefficients

The invention relates to radio engineering and communications, can be used in measurement technology, and is an improvement to the frequency multiplier by author. No. 1443121.

The purpose of the invention is to expand the frequency range of the input signal.

The drawing shows the structure of an electrical frequency multiplier circuit.

The frequency multiplier contains a pulse generator 1, the first 2 and second 3 memory registers, the first 4 and second 5 delay elements, the first 6 and second 7 counters, the divider 8 frequencies with variable division factor, the divider 9 frequencies, the reference generator 10, a code comparison unit 11, a first 12 and a second 13 controlled frequency dividers, a first code setting unit 14 and a second code setting unit 15.

The frequency multiplier works in the following way.

At the beginning of the input signal period, the driver 1 generates a short pulse that goes to the recording inputs of the first 2 and second 3 registers and to the input of the first element 4. The delayed pulse goes to the input of the initial setup of the first 6 and second 7 counters and the first 14 and the second 15 blocks of setting the codes and the divider 8, the division factor of which is K, is set equal to one. The periodic sequence of pulses can be with frequency

F

For

K, K

Jiv

where Kj is the division factor of the divider 9;

 pulse frequency at the output of the reference generator 10.

The pulse from the reference generator 10 is fed to the counting input of the first counter 6. The initial code value at the output of the first block 14 sets the codes N 1. The initial code value at the output of the second block 15

dividing control dividers 12 and 13 without slowing down. This leads to an expansion of the frequency range of the input signal. 1 il.

ten

15

20

25

thirty

35

40

45

55

setting codes N 2 - 2, At the moment of coincidence of the current value of the binary code at the output of the first counter 6 with the binary code at the output of the second block 15 Setting the codes at the output of block 11, a pulse is generated that goes to the setup input of the first counter 6, to the counting input of the second counter 7 and to the counting inputs of the first 14 and second 15 blocks of setting codes. In this case, the first counter 6 is set to the N state, the binary code value at the output of the second counter 7 is doubled (the initial state of the second counter 7 corresponds to one), the output of the first 14 and second 15 code setting blocks is set to - - p

BUT

respectively NI-. 2-1; , where p is the number of pulses from the output of block 11 for the measurement period.

The impulse formed at the output of the block 11 is fed through the second element 5 to the input of the record of the divider 8, the division factor of which is doubled. Thus, the division factor of divider 8 and the value of the binary code at the output of the second counter 7 coincide, and the number of pulses at the output of the reference generator 10 for one period of the input signal K K K K, where K j is the value of the binary code at the output of the first

counter 6.

I

With the arrival of the next pulse from the output of the former 1, the current values of Kj and K binary codes from the first 6 and second 7 counters are written to the first 2 and second 3 registers, 11, respectively, and the first 6 and second 7 counters, the first 14 and second 15, the code setting blocks and the divider 8 are set to the initial state, from which the measurement of the next period of the input signal begins. The division factor of the first controlled divider 12 takes the value Kj, and the division factor of the second controlled divider 13, K / ,. The frequency of the signal at the output of the multiplication frequency can be represented by F "r

foam in the form of F. ,, foot signal F gx

,to

V. og

input frequency

then

F ".K

 K, K,

The division factor of the second controlled divider 13 takes the values K, 1,2,4, ..., 2, and the maximum division factor of the first controlled divider is 12 K, then

og

&

K “P ()

This feature allows to realize high dividing coefficients of the first and second controlled dividers without reducing the speed 10

15

20

VL, which leads to the expansion of the frequency range of the input signal.

Claims (1)

Invention Formula Frequency multiplier auth. No. 1443121, characterized in that, in order to spread the frequency range of the input signal, the first and second code setting blocks are introduced, the first inputs of which are connected to the output of the first delay element, and the second inputs of the first and second code setting blocks are connected to the output of the second delay element, the output of the first code setting unit is connected to the information input of the first counter; the output of the second code setting unit is connected to the second input of the code comparison unit.