SU1529425A1 - Device for gating delayed sampled signals - Google Patents

Abstract

The invention can be used to monitor the varying pulse delay time with respect to clock pulses in radar and information measuring systems. The purpose of the invention is to provide automatic tracking of the delay of the forward signal - by introducing the capacitor 1, the resistor 2, the controlled pulse generator 5, the delay elements 6 and 7, the elements OR 8 and 13, the formers 10 and 14 single pulses, the multiplexer 11. In addition, the device includes a D-flip-flop 3, a shaper 4 single pulses, a counter 9, a register 12, an input bus 15, synchronization pulses, an input bus 16 delayed pulses, an output bus 17. The introduced elements provide automatic tracking of the delay time of the preemptive pulse on the output bus 17 with respect to the signals on the input bus 16 delayed pulses, high speed and high noise immunity. The high speed is ensured by the fact that the tracking of the delay of the anticipatory pulse is carried out according to the results of the previous cycle. In this case, the error in the choice of the delay time of the preemptive pulse does not accumulate from cycle to cycle, which determines the high noise immunity of the device. 1 il.

Description

The invention relates to a pulse technique, in particular, to devices for automatic tracking of the measurement of DU im time delay, and can be used in radar and information measuring systems.

The purpose of the invention is to provide automatic tracking of the forward signal delay.

The drawing shows a functional diagram of the device strobe delayed pulse signals

The gating device of the delayed pulse signals contains a capacitor 1, resistor 2, D-flip-flop 3, Shaper 4 single pulse, controlled pulse generator 5, delay elements 6 and 7, OR element 8, counter 9, second shaper 10 single pulse, m3 liplexer 11, register 12, the element OR 13, the third driver

14 single pulses, input bus

15 synchronization pulses, input bus 16 delayed pulses and output 1 1 7.

The input bus 15 of the synchronization pulses is connected to the S-input of D-flip-flop 3, the input of the first driver 4 single pulses and the input of the first delay element 7, the R-input of D-flip-flop 3 is connected to the input bus 16 of the delayed pulses, C- input through a resistor 2 and D-input - with a common bus, and through a capacitor 1 with a source of supply voltage and inputs of the elements OR 8 and 13, and the output - with a control input of a controlled generator of 5 pulses, the output of which is connected to the counting input of the counter 9, the outputs of which are connected to the inputs of register 12, the reset inputs of the account ika 9 and the register 12 are connected to the outputs of OR elements 8 and 13, respectively, other inputs of which are connected to the outputs of shapers 10 and 14 of the single pulses. The input of the second shaper 10 single pulses is connected to the first output of the first delay element 7 and the recording entry of the register 12. The second output of the first delay element 7 is connected to the clock input of the register 12, its outputs are connected to the control inputs of the multiplexer 11, the output of which is connected to the input the third generator of 14 single pulses and is the output of the device; Switch the four inputs of the multiplexer 1 1

connected to the outputs of the second delay element 6, the input of which is connected to the output of the first shaper 4 single pulses.

The device works as follows.

At the moment of switching on the supply voltage, a short pulse produced by the differentiating circuit consisting of capacitor 1 and resistor 2 sets the D-flip-flop 3, the counter 9 and the register 12 to the initial zero states. This pulse to counter 9 and register 12 is fed through the elements OR 8 and 13,

The impulse arriving at the input bus 15 of the synchronization pulses is applied to the S input of the D flip-flop 3, translating it into a single state. A pulse having an Unstable delay relative to the synchronization pulse arrives at the input bus 16 of the delayed pulses, i.e. to the R input of the D flip-flop 3, and flips it to the zero state. At the exit

D-flip-flop 3 Normalized by a pulse of positive polarity, the duration of which is equal to the delay time of the pulse on the bus 16 relative to the pulse on the 1st 15.

The pulse from the output of the D-flip-flop 3 is fed to the control input of the controlled oscillator 5 pulses. At the output of the controlled pulse generator 5, a burst of pulses is generated,

moreover, the number of pulses in a pack is proportional to the duration of the control pulse. Counter 9 counts the number of pulses in a packet and outputs a code to the inputs of the register 12. G mpuls

synchronization from bus 15 is applied to delay element 7. From the first output of the delay element 7, a pulse is fed to the input of the recording control register 12. At the same time, the delay time of the pulse

from the output I of the delay element 7 should be somewhat longer than the maximum possible delay time of the pulse on the bus 16 of the device relative to the synchronization pulse on the bus 15 of the device. From the output of the first delay element 7, a pulse is fed to the synchronization input of register 12, and the delay time of this pulse must be such that

typesetter register 12 1

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The front coincided in time with and mycls at the output I of the first element of the 7 finishes. A pulse arriving from the second output of the First Delay Element 7 at the register synchronization input overwrites the code corresponding to the delay time on the device bus 16 relative to the synchronization pulse on the device bus 15, from counter 9 to register 12 The recorded code is fed from the outputs

to the control inputs of the mule 1. At the moment of action of the cutoff of the recording resolution impulse coming from the first output of the first delay element 7, the driver of 10 single pulses to form the impulse arriving through the OR element 8 to the reset input of the counter 9. Counter 9 is set to the initial state. A sync pulse from the device bus 15 is fed to a 4 single pulse shaper, which has a gated pulse of the required duration. From the output of the driver, 4 single gating pulses are applied to the second delay element 6. At the outputs of the second delay element 6 there are pulses having different delay times relative to the synchronization pulse on the bus 15 of the device. The outputs of the second delay element 6 are connected to the inputs of multiplexer 11, Multiplexer 11 mu mutes one of its inputs to the output, depending on the code on the control inputs, which is determined by the code from the outputs of the register 12.

Thus, the gating of the pulse present on the device bus 16, having Nes. 1, a time delay relative to the clock pulse. At the time of the cutoff of the gating pulse present at the output of the multiplexer 11, the third single pulse generator 14 generates a pulse that is fed to the reset input of the register 12 via the OR 13 gate, the initial zero state. Further, the operation cycle of the device is repeated.

The device for gating delayed pulses of signals has a high speed, because

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It will automatically monitor the delay of the anticipated impulse based on the results of the previous cycle, and the noise immunity is high, since the error in the choice of the anticipatory impulse delay time does not accumulate from cycle to cycle. This allows the device to be used for automatic tracking of varying delay times in high frequency devices, such as pulse transceiver systems,

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Formula Device

the invention

gating delayed pulse signals containing a D trigger, a counter, a register, an input clock of synchronization pulses connected to the input of the First driver of single pulses, which distinguishes By the fact that, in order to provide automatic tracking of the delay of the anticipatory signal, a capacitor, a resistor, two OR elements, two delay elements, a second and a third single pulse generator, a multiplexer, a controlled pulse generator 0, and an input pulse bus synchronization is connected to the S-input of the D-flip-flop and the input of the first delay element, the R-input of the D-flip-flop is connected to the input pin of the delayed pulses, the C-input of the U-flip-flop is OR to the first inputs of the first and second elements OR, as well as A resistor — with a common power supply bus and through a capacitor — with a power supply voltage; D-trigger input D — with a common power supply; Dtrigger output — with a control input of a controlled pulse generator, the output of which is connected to the counter input of the counter, outputs which are connected to the inputs of the register, the reset inputs of the register and the counter are connected respectively to the outputs of the second and first elements OR, the second inputs of the first and second elements OR are connected respectively to the outputs of the second and third formers of single the pulses, the input of the second single pulse generator is connected to the first output of the first delay element and the control input of the register, the synchronization input of which is connected to the second output of the first delay element.

715294258

register outputs are connected to control hfynbTHruieKCOpa inputs by connecting multiplexer inputs, outputs with corresponding outputs of which are connected to the input of the third and second delay element, the input of which is used for single pulse pulses of the device connected to the output of the first device output bus, information generator of single pulses .

Claims (1)

Formula Device Pulse D-flip-flop, counter, timing of the synchronization pulses, connected to the input of the first single pulses, in general. the fact that, with the automatic delay of the pre-emptive signal delayed, it has a sator, a resistor, two delay elements, single pulse generators, a multiplexer, a controlled pulse generator, and the input clock pulse bus connected to the S-input D of the trigger and the input of the first delay element, R-input The D-flip-flop is connected to the input pin of the delayed pulses, the C-input of the D-flip-flop is connected to the first inputs of the first and second OR elements, and also through the resistor to the common power bus and through the capacitor to the supply voltage bus D-flip-flop D-input - with a common power bus, D-flip-flop output - with a control input of a controlled pulse generator, the output of which is connected to the counter counter input, the outputs of which are connected to the register inputs, the register and counter reset inputs are connected to the outputs, respectively the second and first OR elements, the second inputs of the first and second OR elements are connected respectively to the outputs of the second and third single pulse shapers, the input of the second single pulse shaper is connected to the first output of a delay element and a register recording control input, the synchronization input of which is connected to the second output of the first delay element, the register outputs are connected to the control inputs of the multiplexer, the output of which is connected to the input of the third single pulse shaper and the device output bus, the information inputs of the multiplexer are connected to the corresponding outputs the second delay element, the input of which is connected to the output of the first single pulse shaper.