SU1569879A1 - Device for restoration of clock pulses - Google Patents

Abstract

This invention relates to magnetic recording and can be used in digital data playback devices. The aim of the invention is to improve the accuracy and noise immunity of the device. The device provides recovery of clock pulses, arriving with a repetition period T with an instability following ± 0.25 T. The device generates recovered pulses with a given duration. The change in the state of the outputs of the counter 6 occurs at a time interval equal to the permissible temporal instability of the clock pulses. The second decoder selects the first recovered pulse with a period of T + ΔT, switches the second trigger 7, which rearranges the second decoder 10 to select the period T.

Description

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The invention relates to the field of accumulation of information and can be used in digital data playback devices.

The purpose of the invention is to improve the accuracy and noise immunity.

The device contains a bus 1 input information, the element And 2, the first 3 and second 4 elements OR, bus 5 synchronization, counter 6, the first trigger 7, the generator 8, the first 9 and the second 10 decoders, the second trigger 11 and the inverter 12.

Bus 1 through serially connected element AND 2 and element OR 3 is connected to the output of the device, which is additionally connected to the counting input of trigger 7, the direct output of which is connected to another input of element AND 2. Bus 5 is connected to the first input of element OR 4, the second input of which is connected to the output of the element AND 2, and the output of the element OR 4 is connected to the R-input of the counter directly and through the inverter 12 with the R- input of the trigger 11. The output of the generator 8 is connected to the counting input of the counter 6, the outputs of which are connected to the inputs of the decoders 9 and 10. Exit eshifratora 9 is connected to the S-input of flip-flop 7, and the output of the decoder U - with the S-input of flip-flop 11 and the second input of the OR gate 3, and a direct output of flip-flop 11 is connected to an additional input of the decoder 10.

The device works as follows.

By the zero signal from bus 5, the counter 6 is set to the pulse counting mode of the generator 8. Counter 6 forms a pulse train of duration tboccr with a period T / 4, its outputs have a binary code of the number of quarters of the oscillator frequency period 8. The decoder 9 selects each (3 +) impulse, and decoder Yu - each (5 +) impulse, where N; 0, 1, 2, ... is the number of additional pulses to be restored. Element And 2, whose operation is controlled by trigger 11, is opened at the time of operation

3 decoders 10 tOTK () tQ + -Ј- T +

+ T М M, where tQ is the instant of installation of the counting mode of the counter.6, and is closed by recovered clock pulses coming from the output of the decoder 9 through the element OR 3 to the counting input of the trigger 11

times with

yak

R

 t +

+ T-N J in the absence of clock pulses on bus 1 in the time interval of resolution tpqjp3 / 4, p 5 / 4Т in each period.

When a clock pulse arrives in the time resolution interval, it passes to the device output

5 through the element AND 2 - OR 3, zeroing the counter 6, the trigger 7, the falling edge switches the trigger 11 and closes the element AND 2. The counter 6 continues counting with zero. The process repeats from 0 to the appearance of a single signal on bus 5.

The accuracy of the device is increased due to the fact that errors in the formation of the period during long

5 dropouts in the sync channel. This is due to the fact that the first clock pulse restored with a period of T + dT switches the second trigger, which with its signal rebuilds the second decoder, but does not embrace the period counter. At the same time, all subsequent recovered pulses are formed with a period T. Increasing the duration of the recovered pulse, due to the fact that its formation is not affected by the counter reset circuit, improves the immunity of the device as a whole.

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Claims (1)

Invention Formula A device for clock recovery, containing an AND element, two OR elements, a generator, a counter, a trigger, two decoders, while the generator output is connected to a counter input of the counter, whose outputs are connected to the corresponding decoder inputs, direct output 0 trigger is connected to the first input of the first element AND, the output of the first element OR is the output of the device, the synchronization input of the device through the second element OR is connected to the R input of the counter, characterized in that, in order to improve the accuracy and noise immunity, a second trigger and inverter, with information, 5 15698796 the device input is connected to the second input of the second decoder, the inverse input of the first element I, the output of which is connected to the S input and connected to the first input by the first trigger of the second trigger and the second output of the OR element and the second input. the first element OR, the output of which is the second element OR, the output of which is connected to the counting input of the first through the inverter is connected to the R-input trigger, and the inverse output by the first of the second trigger, the forward output decoder is connected to the S-input connected to the optional first trigger.