SU1647903A2 - Code-to-pulse repetition period converter - Google Patents

Abstract

The invention relates to computing, can be used in digital control systems and is an improvement of the known device described in ed. St. No. 1051705. The purpose of the additional invention is to expand the functionality by providing additional functions for converting code to the duty cycle and phase shift of pulse sequences. The code converter during the pulse repetition period contains a subtracting counter, two valve blocks OR-NOT, five AND elements, an OR element, a trigger, three output buses, and a clock frequency bus. 1 il.

Description

The invention relates to computing, can be used in digital control systems and is an improvement of the invention according to the author. St. No. 1051705.

The purpose of the invention is to expand the functionality by providing additional functions for converting code to a duty cycle and phase shift of pulse sequences.

The drawing shows a diagram of the Converter.

The code converter during the pulse repetition period contains the subtractive counter 1, blocks 2 and 3 of the write gate, the element OR NOT 4, the elements AND 5-9, the tires 10 and 11 of the input code, the element IL AND 12, the trigger 13, the additional output buses 14- 16, the bus 17 clock frequency.

The code converter in the pulse repetition period works as follows.

On tires 10 and 11, codes defining pause and duration, i.e. duty cycle repetition rate.

Suppose that in the initial state in subtractive counter 1, for example, the code of the number N 101 (five) from the bus 10 defining the pause. Bus 17 has no input pulses, the output of the multi-input element OR NOT 4 and the outputs of AND 6-8 are zero levels. Bus 17 is supplied with an input to a sequence of pulses. Counter 1 begins to successively subtract units from the number code entered into it.

When the code is equal to one, the first unit output of counter 1 is set to a single level, which goes to the corresponding input of element AND 5, and the zero levels of the remaining single outputs of counter 1 are present at the inputs of the element OR NOT 4. As a result, the output of the element OR- NOT 4 sets a unit level that unlocks 1/1 5-7 elements. Another fifth v impulse input clock sequence X4 Yu

WITH

TO

From bus 17, it passes through AND 5 to trigger 13 input and through AND 9 open to output bus 16. On the falling edge of the fifth pulse, subtractive counter 1 is set to the zero state, and trigger 13 to the single state. In this case, the zero level appears at the unit 1 first output, and the unit level appears at its first zero output. The output state of the element OR NOT 4 does not change. The unit input levels of AND 7 cause it to trigger, with the result that a signal appears at its output allowing block 3 to write the number code from bus 11 to counter 1. In this case, the recorded code determines the pulse duration in the oscillation period on the output bus 14. Then, similarly to the previous cycle, Counter 1 begins to successively subtract units from the number code entered in it.

When the code is equal to one, the first unit output of the detracting counter 1 is set to a single level and the next pulse passes through the open elements AND 5 and 8 to the output bus 15, and the falling edge of this pulse, the counter 1 and the trigger 13 are set to zero state, as a result After that, after writing the code to counter 1, the element OR NOT 4 returns to its initial state and stops the enabling signal from the output of the element ENTOV And 6 and 7,

Thus, at the output of the trigger 13 and, respectively, on the output bus 14 of the converter, oscillations with a programmable duty cycle are formed, while in the follow-up period the pulse duration and pause are programmed with codes. On the output buses 15 and 16, pulses are generated, the period of which is determined by the code, and the duration is equal to the duration of the clock pulses on the bus 17. At the same time, by changing the code of the pulse or pause, you can change the phase shift between the pulses on the output tires 15 and 16. In addition, the converter, in addition to converting the code to the pulse period, has additional

functions, converting the codes into a pause or pulse duration, as well as into a phase shift between two pulse sequences.

Claims (1)

Invention Formula Code converter in the period of pulse repetition according to auth. St. No. 1051705, which is characterized by the fact that, in order to extend the functionality by providing additional functions converting the code to the duty cycle and phase shift of pulse sequences; the second block of recording gates, the third, fourth and fifth elements AND, the trigger, the second bus of the input code, first, second and third additional output busbars, and an OR element is inserted between the first valve block and the subtractive counter, the outputs of which are connected to the corresponding installation inputs of the subtracting counter, the first inputs to the corresponding outputs of the first recording valve block, and the second inputs to the corresponding the outputs of the second block of recording gates, information the inputs of which are the second bus of the input code, and the enabling input is connected to the output of the third element AND, the first and second inputs of which are combined with the corresponding inputs of the second element AND, and the third input is the first additional output bus, combined with the first output of the fifth And element and connected to the forward output of the trigger, the inverse output of which is connected to the third input of the second And element and the first input of the fourth And element, the output of which is the third additional output bus, and the second input is combined with the second input of the fifth element AND and the counting input of the trigger and connected to the output of the first element AND, while the output of the fifth element AND is the second additional output bus.