SU1285619A1 - Device for stabilizing repetition period of horizontal synchronization pulses - Google Patents

Abstract

The invention relates to an image transmission technique. The purpose of the invention is improving the accuracy of synchronization. The device contains an engine 1, a coding disk 2, a clock generator 3, a time gate generator 4, an inverter 5, three elements 6, 11 and 12, an error counter 7, a generator of a stable frequency 8, a pulse frequency divider 9, a driver of short pulses 10 and OR elements 17. And 13 elements were reintroduced, reversible counter 14, register 15 and switch 16. 1 Il. with

Description

The invention relates to an image transfer technique and can be used to stabilize the horizontal pulse synchronization period in optical-mechanical scanning devices.

The purpose of the invention is to increase the timing of the bone.

The drawing shows an electrical structural diagram of a device for stabilizing the period of following horizontal sync pulses.

The device for stabilizing the period of following horizontal synchronization pulses (Fig. 1) contains an engine 1, a code disk 2, a driver of 3 sync pulses, a driver of 4 time gates, an inverter 5, a second element And 6, a counter of 7 errors, a generator 8 of a stable frequency, a divider

9 pulse frequency shaper

10 short pulses, the first element And 11, the third element And 12, the fourth element And 13, reversible counter 14, register 15, switch

16, element OR 17.

The device for stabilizing the period of the following pulses of horizontal synchronization works as follows.

The pulses from the generator 8 of a stable frequency are counted by the divider 9 of the pulse frequency to the number

L -1

where L is the average string length.

expressed in periods of the frequency of the generator 8 of a stable frequency. The output signal of the pulse-frequency divider 9 starts the shaper of 10 short pulses, which outputs short pulses in succession to three outputs -1, 0, +1 so that the phase of these pulses corresponds to the position of L -1, L and L +1 in the row. The pulses from the output O of the shaper 1 short pulse are output horizontal sync pulses. The switch 16, in accordance with the state of the control inputs, switches to the setting input of the divider 9 pulse frequency one of the read signals: 1, O, +1, or the output signal of the driver 3 sync pulses corresponding to the input pulse of the devices with which it starts the driver 4 temporary gates. The shaper of 4 temporary gates has three slots, the following gates are formed: the strobe -, I start

five

0

five

resulting with the arrival of a pulse of a synchronizer 3 sync pulses; strobe +, starting through the period of the generator frequency 8 of a stable frequency after the end of gate strobe j, strobe L, commencing together with the strobe and ending together with strobe 1. If the pulse from the output O of the driver of the 10 short pulses enters the gate E, it passes through the first element I 11 and sets the error counter 7 to the initial state. In this case, the switch 16 remains in the initial state, and the installation of the pulse frequency divider 9 occurs according to the pulse O of the driver

10 short pulses. If the impulse from the output O of the former 10 short impulses does not enter the gate G, it passes through the first element AND

11 to the counting input of the counter 7 errors. When the number of pulses in the error counter 7 reaches the accumulation number of errors N, a signal is output at its output by switching the 1st switch 16

in such a state that the horizontal synchronization pulse input from the output of the synchronizer 3 sync pulses arrives at the installation input of the pulse-frequency divider 9, thus achieving the initial phasing. Next, an analysis of the output pulse position in the strobe interval 21 is performed. If the impulse O pop5 gives 4 temporary gates to the strobe -former, then it passes through the third element I 12 to the summing input of the counter 14, if it enters the gate 1, then it passes through

0 quarter element AND 13 to the subtracting input of counter 14. When the counter reaches a positive or negative counting limit, 5-s signals appear at the corresponding outputs of the counter, which are at the end of the ZT gate. shaper 4 time gates are written to register 15, which switches switch 16 in such a way that pulses +1 or -1 shaper 10 are connected to the installation input of the divider 9 pulse frequency. short pulses, and also resets the counter 14 to its original state -

5, which provides an accurate phasing step.

The duration of the gates - and +, the magnitude of the accumulation of errors N and the limits of the counting of the counter 14 are selected

128 of a given probability of phase adjustment of horizontal synchronization pulses P during the time T and the distribution density of the instability of the follow-up period of the horizontal synchronization pulses f (x). For the case of the normal distribution of the instability of the period following the input pulse of the horizontal synchronization, the duration of the gates and + is chosen from the ratio

(five ,

where 6 is the standard deviation of the instantaneous phase of the input pulses.

The magnitude of the accumulation of errors and the counting limits of the counter 14 determine the inertia of the device and, therefore, the speed and accuracy of the phasing. To select specific values, it is necessary to follow the statistical parameters of the distribution of the instability of the period following the input pulses of devices.

Claims (1)

Formula invented and The device for stabilizing the period of the following pulses is a horizontal synchronization, containing a motor, with a code disk fixed on its shaft, sequentially connected clock generator associated with a code disk, time gate generator, first AND element and error counter, sequentially connected inverter, whose input is combined with the input of the first element And, and the second element And, the output of which is connected to the installation input of the error counter, are connected in series with a stable frequency generator, Tel and pulse frequency generator of short pulses, and a third AND gate, the output of the generator hundred 0 five 0 five 0 five 0 five 94 The frequency band is connected to the control input of the motor and to the clock input of the time gate generator, and the first output of the short pulse generator is connected to the other inputs of the first and second I elements and is an output of the device, characterized in that Fourth element And are connected in series, a reversible counter, the second input of which is connected to the output of the third element And, a register and a switch, the output of which is connected to the installation input of a frequency divider pulses, as well as the OR element, the first input of which is combined with another control input of the switch and connected to the output of the error counter, and the output connected to the installation input of the reversing counter, the first, second, third and fourth signal inputs of the switch are connected respectively to the switch Vym, second and third outputs of the short pulse generator and the output of the sync pulse generator, the clocking input of which is combined with the clock input of the short pulse generator and connected to the output of the generator a stable frequency, the second output of the time gate driver is connected to the first input of the fourth element I, the second input of which is combined with the first input of the third element AND and connected to the first output of the short pulse generator, the third output of the time gate generator is connected to the second input of the third element And, and the first the output is connected to the register gating input, the second input of the OR element is connected to the output of the register.