SU1185650A1 - Synchronizing generator - Google Patents

Abstract

A SYNCHROGENERATOR, containing a master oscillator, the output of which is connected to the first input of the first frequency divider, the second frequency divider, the output of which is the output of frame clock pulses and connected to the first input of the error signal conditioner, the second input of which is connected to the trigger input and the output of the pulse former, and the first and the second outputs are connected respectively to the first and second inputs of the first reversible counter, the first output of which is connected to the first input of the comparator, and the input of the driver and pulses is the input of the mains voltage, and the trigger output is connected to the first input of the second frequency divider, characterized in that, in order to improve the synchronization accuracy, a second reversible counter, as well as the first and second elements OR, whose outputs are connected to the first and the second inputs of the second reversible counter, the output of which is connected to the second input of the first frequency divider, the third input of which is connected to the second input of the second frequency divider and to the output of the first frequency divider, the second output of the second the frequency divider is connected to the second input of the comparator, the output of which is connected to the first input of the first OR element, the second i output of which is connected to the second output of the first reversible counter, and the first and second inputs of the second OR element are respectively connected to the first output of the second frequency divider and the third output of the first reversible counter.

Description

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Ate 1 The invention relates to television technology and can be used as part of television information display systems. The purpose of the invention is to improve the synchronization accuracy. The drawing shows a structural electrical circuit of the sync generator. The clock generator contains a master oscillator 1, the first 2 and second 3 frequency dividers, trigger 4, the first 5 and second 6 reversible counters, driver 7 pulses, driver 8 error signal, comparator 9, the first 10 and second 11 elements OR. The synchronizer works as follows. At the moment of switching on the supply voltage, the driving oscillator 1 starts operating in a self-oscillating mode, the output pulses of which are divided to the line frequency by the first divider 2 frequencies, and then to the frame frequency by the second divider 3 frequencies. The trigger 4 is set to the zero state, and in the first and second reversible counters 5 and 6, fixed values of codes are inserted (the initial installation circuit is not shown). The code entered in the second reversible counter b is determined from the ratio Ab M -, where M is the counting module of the second reversible counter 6; Ff is the frequency of the master oscillator 1; FC is the frequency of the mains; K is the number of scan lines per one power supply period (vertical scanning period). The value of Ab is defined as an integer with the truncation of the fractional part obtained by dividing. This fractional part is a code A entered in the first reversible counter 5. For specificity, we assume that Fr 28.8 MHz, PC 50 Hz, to 562. Then, using the twelve bit second reversing counter 6, we have M 4096, and therefore , Ae 3076, AS 256. The pulses of the master oscillator 1 are fed to the first frequency divider 2 and gradually increase its content to the maximum value of M, which is 4096 in our case. After this, the next pulse of the master oscillator 1 causes the first divider to overflow 2 as a result of which a horizontal sync pulse is formed at its output, the contents of the second divider 3 frequencies increase by one, and the contents of the second pe02 version of the counter 6 are entered into the first frequency divider 2 (this happens when the sync signal arrives at the third, the first divider 2 frequency input) . The first frequency divider 2 starts the next cycle of counting pulses of the master oscillator 1, but not from zero, but from the number copied to it from the second reversible counter 6. At the same time, the horizontal sweep period at the third output of the first divider 2 frequency will be M - Ae 4096 - 3076 1024 pulses of the master oscillator 1. It is easy to notice that an increase in the code in a reversible counter leads to a decrease in the sequence time of the horizontal sync pulses (FID), and a decrease in the code - to an increase in the duration of the subsequent FID. FID is fed to the input of the second divider 3 frequency, which counts the number of lines in the frame and after accumulation, in this case the number 562, generates a frame sync pulse (XI) arriving at the output of the clock generator. After the synchro generator is turned on by the first pulse with the mains frequency from the output of the pulse maker, trigger 4 is tilted (set to one) and wrapped in the second frequency divider 3, thereby synchronizing the synchro generator with the mains frequency. When the code of the second divider 3 frequency reaches the value K, an XI is generated at its output, arriving at the first input of the error signal generator 8, to the second input of which a pulse arrives from the output of the signal generator 7 pulses. Assume that, after phasing the synchro-generator, the pulses at both inputs of the driver 8 of the error signal came simultaneously. Then the pulses at its outputs are not in TC, and the contents of the first reversible counter 5 will remain unchanged and equal to AS 256. In the considered example, the sequence of horizontal sync pulses is M - Ab 1024 minimum image sampling steps (periods of the master oscillator 1). However, lines with a duration of only 256. After the contents of the second divider 3 frequency reaches a value of 256 (code recorded in the first reversible counter 5), the output of the comparator 9 is a pulse that through the first element OR 10 arrives at the first summing input the second reversible counter 6 and increases its content by one. This leads to the fact that the two subsequent raster lines have a duration not in 1024, but in 1023 periods of the master oscillator 1, i.e., their length in our case is reduced by 37 ms. At the end of the frame, when the last line is formed, the frame clock from the output of the second divider 3 frequencies through the second element OR 11 restores

the contents of the second reversible counter 6 (decreases by one), resulting in the next frame the first 256 lines as in the first frame have a duration of 1024 periods of the frequency of the master oscillator 1, and the subsequent - 1023.

If the CSI arrives at the first input of the imager 8 of the error signal later than the pulse from the imager of 7 pulses, then it is obvious that the period of frame pulses must be reduced. This process is as follows.

At the second output of the error signal generator 8, a pulse is generated, reducing the content of the first reversible counter 5 by one. As a result, 255 lines with a duration of 1024 samples were formed in the next frame, and the remaining B lines were 1023 samples. Therefore, the period of the frame sync pulse is reduced only by one minimum image sampling step (by one period of the frequency of the master oscillator 1). If, in the next frame, the temporal ratio of the control pulses at the inputs of the deviation signal generator is maintained, i.e. the CSI arrives later, the automatic regulation continues. and the length of the frame scanning period is reduced by another period of the frequency of the master oscillator 1.

Consider the case when the mismatch between the specified control pulses is so large that it leads to a reduction in the content of the first reversible counter 5 to zero. Moreover, all the raster lines have the same duration equal to 1023 periods of the frequency of the master oscillator 1. The next pulse from the output of the error signal generator 8, which reduces the contents of the first reversing counter 5, causes the appearance of the code 562 and the formation of a transfer pulse at its second output, which, through the first element OR 10, enters the first input of the second reversible counter 6 and increases its contents by one, which in this case corresponds to the code of the number 3077. Since in the first reversing center tchike 5 at this point contains the number 562, then all rows as before have a duration of the driving pulse 1023

Oscillator 1. (It should be noted that for accurate operation of the device, it is necessary that the frame sync pulse arrives a little later than the impulse to output the comparator 9. The required delay of several tens of nanoseconds is provided by the natural signal delay in the chips used, therefore the delay element itself in the drawing not shown). In this case, at the end of the frame (after line 562), the contents of the second

0 of the reversing counter 6 is increased by one according to the signal from the output of the comparator 9, and then immediately reduced to the previous value by the frame sync pulse.

If the network frequency continues to increase, then the next pulse from the output of the error signal generator 8 subtracts one from the contents of the first reversing counter 5, resulting in the next frame contains 561 lines, 1023 samples long, and one line, 1022 times long

Q discrete, i.e. the device works as before.

The clock generator works in the same way when the mains frequency decreases. At the same time, the content of the first reversible counter 5 is sequentially increased by one with each arrival of a pulse from the output of the pulse shaper 7, which leads to an increase in the XI following period each time by one increment. After accumulating in the first reversible counter 5 the number 562 the next pulse

 generates a transfer signal, which through the second element OR 11 is fed to the second input of the second reversible counter 6 and reduces its content by one, and in the first reversing counter the content becomes equal to zero. With the arrival of the next control pulse in the next frame, one has a duration of 1025 samples, and the rest 1024.

Thus, at any time in the process of tracking the frequency of the supply

0 network, the proposed synchronizer provides the formation of horizontal sync pulses, the duration of which differ by no more than one period of the frequency of the master oscillator 1. This difference is not detected at all on the display screen, since it falls on the return time of the beam along the line.

Claims (1)

A sync generator containing a master oscillator, the output of which is connected to the first input of the first frequency divider, the second frequency divider, the output of which is the output of the frame clock and connected to the first input of the error driver, the second input of which is connected to the trigger input and the output of the pulse driver, and the first and the second outputs are connected respectively to the first and second inputs of the first reversible counter, the first output of which is connected to the first input of the comparator, while the input of the pulse shaper ov is the voltage input of the mains supply, and the trigger output is connected to the first input of the second frequency divider, characterized in that, in order to improve the accuracy of synchronization, a second reversible counter is introduced, as well as the first and second OR elements, the outputs of which are connected to the first and second inputs the second reverse counter, the output of which is connected to the second input of the first frequency divider, the third input of which is connected to the second input of the second frequency divider and with the output of the first frequency divider, the second output of the second divider It is connected to the second input of the comparator, the output of which is connected to the first input of the first OR element, the second § output of which is connected to the second output ι of the first reversible counter, and the first If and the second inputs of the second OR element are connected respectively to the first output | v of the second divider frequency and the third output of the first reversible counter. 5 ssi Network * 7