SU1753487A1 - Device for shaping chromatic signals of graphic image - Google Patents

Abstract

Usage: automation and computing technology, information display systems on the television indicator screen. The invention: the device contains counters 1, 2, 3 ,. blocks 4 and 5 of RAM, blocks 6, 7 comparison, switches 8, 9, register 10, trigger 11, elements OR 12, 13, elements 14, 15, 26, element 16, elements 7, 24 of delay, driver 25 momentum. 1 il.

Description

The invention relates to automation and computer engineering and can be used in information display systems on a television indicator screen. 5

The purpose of the invention is to increase the speed of the device.

The drawing shows a structural diagram of a device for generating color signals of a graphic image. 10 The device contains the first 1, second 2, third 3 counters, the first 4 and second 5 blocks of RAM, the first 6 m, the second 7 comparison blocks, the first 8 and second 9 switches, register 10, trigger 11, the first 15 and 12 13 elements OR, the first 14 and second 15 elements AND, element NOT 16, the first delay element 17.

Positions 18-23 indicate the inputs of the respective blocks. 20

The device also comprises a second delay element 24, a pulse shaper 25, and a third AND element 26.

The device operates in two modes: the mode of generating signals of the graphic 25th image of frames already contained in the memory (playback mode), and the mode of recording information about new frames (replacing old ones or adding new ones to those already stored in memory) with simultaneous playback information about the new frame on the indicator.

In any mode, the beginning of work with the next frame is set by the clock pulse at input 18, the end is set by the pulse from output 35 of the third counter 3.

Consider the operation of the device in playback mode. In this mode, at the control input (mode input) 23, the signal value is zero. 40

At the moment of time, in phase with the beginning of the frame scan (indicator - a television tube), a signal of the starting address of this frame is supplied at input 19. This signal is fed to the address inputs of 45 blocks 4 and 5 of the memory. The number of addresses allocated in any mode for a certain frame is selected to be the maximum for a given set of frames (in the most general case, it can vary for some sets of frames from one for monotone - monochromatic frames to a number corresponding to the image dimension at the raster points). For most real frames, the number of addresses in block 55 encoding of a raster array is much less than the number of image frames.

Counter 1 iterates over the addresses; related to this frame. At the beginning of the scan of the next frame, a code is entered into it at the initial address of this frame. Clock pulses at the input 21 correspond (in frequency) to the repetition rate of image elements (dots, pixels) during the direct course of the beam in the raster. Counter 2 generates an address code for an image element in a strip, counter 3 generates a common (in a frame) number of an image element and gives a signal about the end of a frame. The RAM block 4 is intended for storing η-bit codograms containing information about the color (brightness) of the strip. Block 5 RAM contains information about the lengths (in the number of elements - points) of the bands.

In the playback mode at the initial moment of formation of the frame, the counter 1 is recorded at inputs 19 the initial address of this frame. At the input 23, there is a zero potential, which, arriving at the switches 8 and 9, ensures such a connection that the outputs (η-bit color code (luminance) of the strip) of block 8 are switched to outputs 22, and the output of block 6 is switched to the output of block 9 Switch 8 is a series of n-one-bit switches of the block 9 type, in which the control inputs are combined. In addition, comparison blocks 6 and 7 form a single signal at the outputs if the input binary codes are equal and zero in all cases of their inequality.

With the installation of the trigger 11 in a single state, the synchronization pulse of the beginning of the sweep to the device begin to receive clock pulses through the element And 15. With the beginning of the first line of the frame at the outputs 22 of block 8, a color code (brightness) of the first strip of the frame from block 4 appears, and at the outputs of block 5, a code for the length of the strip. Counter 2 counts clock pulses. As soon as the codes from the outputs of blocks 2 and 5 coincide, a positive signal is taken from the output of block 6 and, through switch 9, resets counter 2 and increments counter 1, forming the next frame address, i.e. a codogram of color (brightness) at the output of block 4 of the next (second) strip and its length from the outputs of block 5.

Thus, the process continues for all addresses of a given frame. At the end of the frame, the output signal of counter 3 last is reset, and counter 2 and trigger 11 are also set to zero. Due to the presence of a zero signal at one of the inputs (mode input) of element 14 26, the write signal to blocks 4 and 5 in this case is not formed.

Then, the code of a new (or the same) frame is received at the inputs 19, which captures a new display cycle by the start signal from output 18. The signals for setting the starting address at the inputs 19 are in phase with the frame scan start signals (signal from input 18).

The remaining nodes do not affect the operation of the device in playback mode.

Consider the operation of the device in recording mode. At the same time, during the entire scan time of the frame, a positive signal is received at input 23 (in contrast to the playback mode), fixing the recording mode 10. He switches the switches 8 and 9 so that the signals from the inputs 20 are connected to the outputs 22, and the output of the shaper 25 is connected to the output of the switch 9.

During the frame (new), the color (brightness) codegrams of the new recorded frame from the scanning device (not shown), for example, from a recording television tube or other device, in digital form, 20 whose parameters (length of horizontal and vertical scanning, number various coded colors (brightness) of the image, etc.) similar to the parameters of the displaying television indicator.

The current information received at inputs 20 in the form of the current color code (brightness) of the scanned image is sent to outputs 22 directly and to the information inputs of register 10. At inputs 19 of block 1, its (frame) initial address is formed at the beginning of the recorded frame, as in the playback mode .

The start pulse of the frame at input 18, similarly to the playback mode, sets trigger 11 to a single state. The signal from the direct output of the trigger 11 opens the element And 15 and the clock starts to receive pulses from the input 21,

The signal from input 18 also comes through the OR element 13 to the input of the register register 10, where the initial (hereinafter - the current) color code (brightness) is set. The signal from the direct output of the trigger 11 through the delay element 17 is delayed on it and, not arriving at the initial moment (before the first codogram is written to register 10) at the input of the And 14 element, it prohibits the passage of Not equal to a unit 50 value at the output element NOT 16 at the first moment of recording a new frame. This prevents the recording of any information (not needed) in blocks 4 and 5 at the beginning of the frame (until the end of the 55 first band). At the initial section, the codogram of the first band at the input 20 and at the outputs of the register coincides, and a positive signal is taken from block 7 Equal to. When changing the codogram at the next point of the frame (changing the color of the image signal, the beginning of a new band) at the inputs 20, the comparison unit 7 generates a zero signal, which through the element HE 16 (transforming into a 5 positive signal) and through the AND element 14 according to the resolution signal from the element 17 delays and through the shaper 25, through the switch 9 and the OR element 12 generates a narrow write pulse to blocks 4 and 5, in which the color (brightness) codegram and the length of the ended strip, respectively, are written from blocks 10 and 2. Recording from register 10 into a block of 4 colors (brightness) of the ended strip, 15 since the register 10 is triggered with some natural delay.

The same signal (from block 7) enters through the delay element 24 and the OR element 13 to the register entry, recording the value of the new color (brightness) codegram from the inputs 20. The same signal, coming through the OR element 12, resets counter 2 and increments counter 1. Thus, the analysis of the data of the new 25 color (brightness) codegram begins.

Thus, the device works until the end of the frame. At the end of the frame, the counter 13 gives out a pulse, resets itself, sets the trigger 11 to the zero state and gives a signal about the end of the frame to the element OR 12. but this signal records the color code (brightness) and the length of the last frame strip and the counter 2 is reset.

The device is ready for further work in any mode.

Thus, the claimed device allows how to generate color signals of the image (graphic) of existing new frames (or replacing old frames with new ones) also at the request of the user, without interrupting the display of information and allowing simultaneous recording to control (visual) the recorded frame45 by combining recording and displaying the generated image on a television indicator, which increases the recording speed without requiring special devices, and the organization of individual processes, provides the continuity of the display of information on the indicator.

Claims (1)

Claim A device for generating color signals of a graphic image containing the first and second counters, the installation input of the first counter is the input of the initial address of the device, the outputs of the first counter are connected to the address inputs of the first and second blocks of RAM, the outputs of the second block Ί RAM is connected to the information inputs of the first group of the first comparison unit, the information inputs of the second group of which are connected to the outputs of the second counter, characterized in that, in order to improve the speed of the device, it contains a second comparison unit, a trigger, the installation input of which is a device sync input, the first, second and third elements And, the first input of the second element And is the clock input of the device, the second input is connected to the direct output of the trigger, the first and second delay elements, t third counter, first and second elements OR, register, first and second switches, element NOT and a pulse shaper whose output is connected to the first information input of the second switch, the second information input is connected to the output of the first comparison unit, the control input of the second switch is the control input of the device connected to the control input of the first switch and the first input of the third AND element, the second input of which is connected to the output of the first OR element, connected to the reset inputs of the first and watts Of the second counters, the outputs of the second counter are connected to the information inputs of the second RAM block, the information inputs of the first RAM block are connected to the register outputs connected to the information inputs of the first group of the second comparison unit, the information inputs of the second group of which are information inputs of the device connected to the information inputs register, the control input of which is connected to the output of the second OR element, the first input of which is connected to the device sync input, and the second input through the second delay element with the output of the first element And connected to the input of the pulse shaper, the first input of the first element And is connected to the output of the element NOT, the input of which is connected to the output of the first comparison unit, the second input of the first element And is connected through the first delay element to a direct trigger output, the reset input of which is connected to the output of the third counter connected to its reset input and the first input of the first OR element, the second input of which is connected to the output of the second switch, the inputs of the first group of the first switch are connected to the information inputs of the device, the information inputs of the second group are the outputs of the first block of RAM, and its outputs are the information outputs of the device, the output of the third element And is connected to the control inputs of the blocks of RAM, the output of the second element And is connected to the counting the inputs of the third and second counters.