SU1005170A1 - Device for displaying information on crt screen - Google Patents

Description

(54) DEVICE FOR DISPLAYING INFORMATION ON SCREEN ELECTRON-BEAM TUBE

one

The invention is related to automation and computing and can be used in the construction of devices for forming symbols on a screen of a cathode ray tube (CRT). A device for displaying information is known, which contains a pulse generator, a synchronization pulse shaper, a symbol memory,; an address counter, a logic unit, a code-time converter, a micro-command register, a function voltage generator, a beam illumination unit, a frequency divider, two triggers , multivibrator, symbol element selection block 1.

A disadvantage of this device is that it allows displaying only those symbols for which a program is specified in its memory block.

The closest to the proposed technical entity is a device for displaying information, containing a memory block connected to a register, a function voltage generator connected to a register, a code converter — time connected to a pulse generator, a register connected to a beam illumination unit an address counter, a logic unit and a pulse shaper connected to a pulse generator, a code-time converter, a function voltage generator, a memory unit, an address counter, and a logic m unit connected to the block memory address counter and connected to the code- time converter and memory unit 2.

The disadvantage of this device is that it displays only the characters stored in its memory block.

The purpose of the invention is to increase the information content of the displayed information {by displaying the same symbol stored in memory, of various types, with lines, for example, solid, dotted, dashed, etc.).

The goal is achieved by the fact that the device containing the series-connected block of elements 2И-OR, the address counter, the memory block, the register and the sweep voltage generator connected to the CRT deflection systems are connected in series. pulse generator, synchronizer and converter code — time and a backlight unit connected to a CRT modulator; the outputs of the synchronizer are connected to a block of 2I-OR elements, an address counter, a memory block, a code-time converter, and a generator of scanning voltages; time is connected to the synchronizer and the register, serially connected frequency divider, pulse width former and element 2И-OR and trigger are input, frequency divider input is connected to the pulse generator, output of element 2И-OR connected to the backlight unit, and the inputs of the element 2И - OR are connected to the outputs of the register and the trigger, respectively, the inputs of the trigger and the frequency divider are connected to the outputs of the synchronizer.

FIG. 1 shows a block diagram of the device; in fig. 2 - type of generated characters; in fig. 3 - block diagram of the elements of the 2I - OR; in fig. 4 is a block diagram of a synchronizer.

The device contains a pulse generator 1, a synchronizer 2, a block 3 of elements 2И —OR, an address counter 4, a memory block 5, a code-time converter 6, a register 7, a generator of 8 sweep voltages, a backlight unit 9, a frequency divider 10 (controlled ), pulse width generator 11, trigger 12, 2I-OR element 13, device inputs and outputs 14-21, respectively, pulse distributor 22, symbol end signal generator 23, symbol push driver 24, reversal signal generator 25, trigger 26 and elements 27 and 28 2I - OR.

The pulse generator 1 is connected to the synchronization input 15 by the control input, the zero input is connected to the zero input of trigger 13, the code-time converter 6, the frequency divider 10, the sixth synchronizer output and the device output 21, the generator 1 output is connected to the first input of the synchronizer 2, the first output of which is connected to the control input of the block 3 of the elements 2I-OR, the output of which is connected to the information input of the counter 4 addresses, the reset input of which is connected to the second output of the synchronizer 2, and the output to the address input of the memory block 5, the third, fourth and fifth outputs of the synchronizer 2 are connected to the synchronous inputs of the memory 5 block, the scan generator 8 and the code-time converter 6, respectively, the second synchronizer input is connected to the counting input of the address counter 4, the control input the register 7 and the output of the code-time converter 6, the information input of which is connected to the information inputs of the synchronizer 2, the register 7, the output of memory block 5 and the second information input of the block 3 of the elements 2И-OR, the first information input of This is the first information input 14 of the device, the output of the register 7 is connected to the information input of the sweep generator 8, the third and fourth inputs of the element 13 2I-OR, the output of which is connected to the input of the backlight unit 9, the second and fifth outputs of the element 13 2I-OR are connected with the first and second outputs of the trigger 12, respectively, and the first input with the output of the pulse width generator 11, the second input of which is connected to the output of the frequency divider 10, the second input of which is connected to the output of the pulse generator 1, the first inputs of the divider 10 The frequency, the pulse width generator 11, and the trigger 12 are inputs 16-18 of the device, the device output 19 is the output of the sweep generator 8, and the device output 20 is the output of the beam illuminator 9.

The pulse generator 1 is designed to form the burst of clock pulses necessary for the operation of the synchronizer 2.

The synchronizer 2 is designed to form synchronization and control signals between the units of the device. Its technical implementation can be carried out according to the block diagram shown in FIG. four.

Unit 3 of the elements 2I-OR is a switch of information from two directions and is intended for switching the symbol code from the input 14 of the device or the starting address code from the output of memory block 5. Its technical implementation can be performed on elements 2I-OR according to the block diagram shown in FIG. 3

The address counter 4 is designed to control the address code at the input of the memory block 5, which is designed to record and store initial address codes and character vector codes.

The code-time converter 6 is intended to form the signals of the end of the symbol vector. Its technical implementation can be carried out on the basis of 133 (155) IE7 microcircuits in the subtraction mode.

Register 7 is designed to record and store character vector codes at the time of their formation, sweep generator 8 to form functional stresses of the character sweep along the X and Y coordinates.

The illumination unit 9 is intended to form the illumination signals of the vector contours of the symbol necessary for its representation on the CRT screen.

Frequency divider 10 is used to change the clock frequency at its output with an external control code. Its technical implementation can be carried out, for example, on the basis of 133 (155) IE8 microcircuits.

The pulse width shaper 11 is designed to generate signals for highlighting the vectors of the symbol in duration.

The device works as follows.

The symbol code from the device input 14 is fed to the first information input of the block 3 of the elements 2I-OR, and at the input 15 a start-stop generator of 1 pulses is triggered by a synchronization pulse. From the output of generator 1, a packet of clock pulses goes to the first input of synchronizer 2, which at the first output generates a signal for recording the character code through block 3 of elements 2И-OR to counter 4 of the address, and at the third output is a signal to access memory block 5. The recorded character code in counter 4 is an address for selecting the code of the initial address of the character firmware from memory block 5.

The symbol firmware consists of the starting address code, vector codes, and the character end code. Each input character code has its own initial address code, which is the code address of the first character vector.

The selected starting address code from memory block 5 is stored in its output register (not shown). After sampling the starting address code from memory block 5, the address counter 4 is set to zero by a reset signal from the second synchronization output, a mash, which at the first output generates a enable signal for writing the starting address code through block 3 of the elements 2И— OR to counter 4, and at the third output, a second access signal to memory unit 5.

Based on the starting address code and the second reference, the output of memory block 5 generates the code of the first symbol vector, which has the following structure: 6 bits to control the vector sweep along the X and Y coordinates, 3 bits to set the vector length and 1 bit for forming the illumination signals.

After sampling the code of the first vector of the symbol from the memory block 5, clock pulses start to come from the fifth output of synchronizer 2 to the synchronous input of the 6-time-converter, and to its information input - 3-bit code of the vector length from the output of memory block 5.

At the initial moment of time at the output of the code-time converter 6 a vector end signal (SCR) is generated, corresponding to a zero-length vector. According to this signal, the vector length code is entered into the code-time transducer 6, and the sweep code and the highlight symbol code are entered into register 7.

At the same time, this signal arrives at the counting input of the counter 4 addresses and increases its state by one. In addition, by this signal, on the fourth meter, on the synchronizer clock, a signal is generated to enable the operation of the sweep generator 8, and on the third output the next signal is addressed to the memory block 5.

According to the modified code of the starting address and the new address, the code of the second symbol vector is stored at the output of the memory block 5, which is stored in its output register.

Since the writing of the code of the first vector in the register 7 and the converter 6 code-time

The symbol sweep generator 8 generates sweep voltages along the X and Y coordinates, the code-time converter 6 sets the length of the vector, and the backlight unit 9 determines the brightness of the Eept beam.

After the formation of the first

0 of the vector of the symbol at the output of the converter, l 6 code-time, the signal is formed by the hard current. a time interval proportional to the frequency of the clock pulses at the sync input and the 3-bit code at the information input. With this signal, the code of the second symbol vector from the output register of the memory block 5 is entered into the register 7 and the code-time converter 6. From this point in time, the sweep generator 8 generates the sweep voltages of the second vector symbol along the X and Y coordinates, and the code-time transducer 6 sets its length.

Similarly, all subsequent vectors constituting the character shape are formed. When forming the last vector

5 characters) 1a at the output of the memory block 5, an output number is formed containing zeroes in all bits. Three bits of this number are fed to the information input of synchronizer 2, which, with this code and the last SCR, forms the end-of-symbol signal. This signal brings the device to its initial state and enters the output 21 of the device to call the code of the next character from an external control device (not shown).

5 Simultaneously with the symbol code, the sign of the line type of the displayed symbol arrives at the input 16 of the device, the stroke length code is input to input 17, and the interval between strokes is input to input 18.

At zero level, the input of the device 16 at the second output of the trigger 12 sets the level of the logical unit, which allows the illumination signals to pass from the fourth input of the 13 2I-OR element to its output. In this case, the illumination signals with a duration equal to the time interval between the pulses of an SLE come to the input of the light block 9. In this case, the symbol on the CRT screen is displayed in continuous line segments, the backlight of which is determined only by the backlight code from the output of memory block 5 (Fig. 2, option I).

Upon receipt at the input 16 of the device characteristic line (signal of the logical unit), the trigger 12 is set to one

condition. The level of the logical unit at its first output allows the passage of illumination signals from the third input of element 13 2I-OR to its output. At the output of the element 13, the light pulses are modulated by the duration of the pulses arriving at its first input from the output of the pulse width generator 11, and the symbol is displayed by a dashed line, the length of the strokes of which is determined by the pulse width at the output of the driver 11.

The output pulse duration of the imager 11 is controlled by a code at the device input 17, and its start is controlled by pulses from the output of the controlled frequency divider 10, which changes its frequency according to the code at the device input 18. The frequency at the output of divider 10 determines the interval between the beginnings of two adjacent strokes, i.e. their step.

By specifying, in certain combinations, the codes at the inputs 16-18 of the device, it is possible to change the appearance of any character recorded in memory block 5.

For example, if it is necessary to display a symbol in dots (Fig. 2, variant II), then a logical unit is fed to the device input 16, a code corresponding to the minimum duration of the output pulses of the imaging unit 11 is fed to the input 17, and the code defining the required distance is input 18. between points.

Claims (2)

1. Author's certificate of the USSR 711602, cl. G 06 K 15/20, 1980. 2. USSR author's certificate 634322, cl. G 06 K 15/20, 1978 (prototype). Gn , n