SU1088060A1 - Device for generating characters - Google Patents

Abstract

A DEVICE FOR FORMING NW MVOLS containing a pulse generator, one of whose inputs is connected to the first input of the device, the other input to the first output of the device, to the first input of the counter and to the first output of the control unit, the second output of which is connected to the first input of the element block ZI-OR, the second input of which is connected to the second input of the WA devices, the third input of the ZI-OR unit is connected to the output of the first memory block, with the first inputs of the converter the code — time, register and control unit,. the second input of which is connected to the output of the pulse generator, the third input - with the output of the converter at the time, the second register and counter inputs, the third input of which is connected to the output of the ZI-OR element block, the output of the counter is connected to one of the inputs of the first memory block ti, the other input of which is soeken with the third output of the control unit, the fourth output of which is connected to the second input of the code-time converter, the fifth output - to the first input of the sweep generator, the outputs of which are connected to the second and third outputs of the device Actually, the second input of the sweep generator is connected to one of the outputs of the register, the other output of which is connected via the backlight unit to the fourth output of the device, characterized in that, in order to expand the field of application of the device by changing the nomenclature and configuration of characters without changing the input code or replacing the block ( L ka memory, it contains the second memory block, a trigger, and the second elements And, the outputs of the first and second element And are connected to the quarter and the left inputs of the block of elements ZY-OR, the sixth input of which is connected With the output of the second memory block, the inputs of which are connected to the first and second inputs of the device, the third input of the device is connected to one of the trigger inputs, the other input of which is connected to the first output of the control unit, the sixth output of which is connected to the first input of the first and The second input element, the second input of the x-ory, is connected to the trigger outputs.

Description

The invention relates to automation and computing and can be used in the construction of devices prior to the display of symbols on the screen of a cathode ray tube. A device for displaying information is known, comprising a pulse generator, a clock counter, a memory block, a symbol selection decoder, a vectorforming register, a control trigger, an encoder, X and Y coordinate counters, an interrupt decoder 1. A disadvantage of the device is its application, associated with the need to change the symbol selector and interrupt decoder patterns when changing the number of generated symbols. It is also known a device for displaying information, comprising a pulse generator, a pulse shaper logic unit, an address counter, a memory unit, a code-time converter, a micro-command register, a function voltage generator, a backlight unit, a controlled frequency divider, a L2 trigger. It is impossible to: a u the alphabet of generated characters without changing the input code. The closest in technical terms to the proposed technical solution is a device for displaying information, containing a memory block, connected. with a register, function generator, connected to a register, code-time converter connected to a pulse generator and register, connected to an illuminator block, address counter, logic unit and pulse driver connected to a pulse generator, code-time converter , a generator of functional voltages, a daddy unit, an address counter and a logic unit connected to a memory unit and a counter connected to a code-time converter and a Sz1 memory unit The disadvantage of the known devices is the impossibility of varying the prefecture klatury or characters without changing the configuration code vhodnoto Single plaques or replacement memory which reduces the functionality of the device object of the invention is to expand the functional capabilities tron devices. The goal is achieved by the fact that the device containing a pulse generator, one of the inputs of which is connected to the first input of the device, another input - to the first output of the device, to the first input of the counter and to the first output of the control unit, the second output of which is connected to the first input of the unit ZI-OR elements, the second input which is connected to the second input of the device, the third input of the ZI-OR element block is connected to the output of the first memory block, with the first inputs of the code-time, register and control unit inputs, the second input which is connected to the output of the pulse generator, the third input with the output of the code-time converter, the second inputs of the register and the counter, the third input of which is connected to the output of the ZI-OR element block, the output of the counter is connected to one of the inputs of the first memory block, the other input is connected with the third output of the control unit, the fourth output of which is connected to the second input of the converter at a time — the fifth output — to the first input of the sweep generator, you:; which are connected to the second and third outputs of the device, the second input The generator is deployed and connected to one of the register bits, the other output of which is connected through the illumination unit to the fourth output of the device, the second memory block, the trigger, the first and second elements AND, the outputs of the first and second elements AND are connected to the fourth and fifth inputs of the ZI-OR block, the sixth input of which is connected to the output of the second memory block, whose inputs are connected to the first and second inputs of the device, the third input of the device is connected to one of the trigger inputs, another input; which is connected to the first output of the control unit, the sixth output of which is connected to the first input of the first and second elements AND, the second input of which is connected to the trigger outputs. FIG. 1 shows a block diagram of the device; in fig. 2 is a pulse generator circuit; in fig. 3 is a control block diagram; in fig. 4 shows a code-time converter circuit; figure 5 - block diagram of the elements ZI-OR. The device contains a pulse generator 1, a control unit 2, a block. EZ-OR elements, a counter 4, a first memory block 5, a code-time converter 6, a resistor 7, a sweep generator 8, a backlight unit U 3108, the first element I O, the second element 11, the trigger 12, the second memory block 13, the first 14, the second 15 and the third 16 inputs of the device, the first 17, the second 18, the third 19 and the fourth 20 outputs the device The pulse generator 1 contains a trigger 21, the element 22 And line 23 delay ki. The control unit 2 contains a signal conditioner 24, a reference signal conditioner 25, a pulse generator 26, a trigger 27, a reset generator 28 Code converter 6 - time contains a counter 29 and an AND 30 element. And -OR. The device works as follows. The code of the symbol from the input 15 of the device is fed simultaneously to the first information input of the block of 3 elements OR and the address input of the block of 13 memory. The characteristic of the character characteristic (e.g., uppercase or lowercase) through the inputs 16 of the device enters the first input of the trigger 12. A synchronization pulse from the input 14 causes the device to start the pulse generator 1 and interrogate the memory block 13. Pulse generator 1 forms a burst of clock pulses within a symbol generation time. From the output of the generator 1, the pulses arrive at the first input of the control unit 2, which at the first output generates a signal for writing the symbol code. This signal arrives at the first switching input of block 3 of the ZI-OR elements and allows the character code to pass from the first information input of block 3 to the information input of counter 4. The character code is written to counter 4 and from its output goes to the address input of block 5 of memory. If the generated (uppercase) character has an additional characteristic (lower character), then memory 13 is excited by its code, memory 13 is generated at the output of which is the code for the initial microprogram building address of the lowercase character recorded in memory 5. This information enters the second information input of the block 3 ZI-OR elements. The firmware of each character consists of the starting address code, vector codes, and the character end code. Symbols 0 with two characteristics have two initial addresses, which are located in two memory blocks. In block 5 of memory, codes of initial addresses of characters with the first characteristic (upper case characters) are placed, and in block 13 of memory, only codes of initial addresses of characters, an additional characteristic (lower case characters) are placed. The codes of the start addresses in memory block 5 form the first information array. The address of each information cell in this array corresponds to the input character code. Vector codes and character end codes form the second information array in memory block 5. The code of each vector of a symbol is shifted by one address relative to each other. The order of location of the vector codes in the microprogram of the symbol corresponds to the order of their connection to the CRT screen. After the code of the last vector of the symbol, it places the zero code defining the end of the symbol firmware. After this code, the firmware of the next character is placed, and so on. The addresses of the first vectors in the postscoding firmware, no symbol correspond to the codes of the initial addresses of the characters. Symbols that have two characteristics (for example, uppercase and lowercase) have two build microprograms, which are located in the second array of memory block 5 at arbitrary addresses. The address of the first vector of the symbol with the second characteristic (lower case symbol) corresponds to the code of the initial address of the symbol recorded in memory block 13. Simultaneously with the arrival of the symbol code from the output of the counter 4, the first access signal from the second output of the control unit 2 is received at the second input of the memory block 5. The selected information on the symbol code and the first call, which is the code of the starting address of the symbol with the first characteristic, goes to the third information input of the 3 ZI-OR elements block. After / this, the control unit 2 at the third output generates records of the initial address, which goes to the first inputs of the elements AND 10 and 11. The second inputs of these elements from the output of the trigger 12 receive single or zero levels. If at the input 16 of the device the character attribute corresponds to the zero level (uppercase character), then the second input of the And 10 element from the inverse output of the trigger 12 receives a unit level that allows the signal to pass through the And 10 element to the third switching input of the 3 ZI element block -OR. By this signal, the code of the initial address of the generated symbol passes through block 3 of the ZI-OR elements and is rewritten into counter 4, Element 11 is closed with zero from the direct output of trigger 12 and blocks the recording signal to the second switching input of block 3 OR. The zero level of the signal at the output of the AND 11 element blocks the passage of information through the block 3 of the ZI-OR elements and from the output of the block of 13 memory. After the code of the starting address is written into the counter 4, the control unit 2 ffms the second access to the memory block 5. According to this reference and the code of the initial address from the output of the counter 4, the block 5 pakmti forms the code of the first symbol of the wave from the selected microprogram of its construction. This code is stored in the output register of memory block 5 (not shown). . Symbolic vector codes, for example, have the following structure: 6 bits are designed to control vector scanning in the X and Y coordinates, 3 rows to set the vector length and one bit to form a vector illumination signal on the CRT screen. After sampling the code of the first vector of the symbol from the block 5 of the memory from the quarters of the output of the eye 2 of the control, clock pulses are sent to the synchronous input of the converter 6, the code is time, and its information input is a three-bit code length of the vector from the output of the block 5 of memory, Time Converter 6 coa - time generates an input signal by which the vector length code is entered into its counter, and the sweep code and light code into the register 7. The same signal enters the counting input of the counter 4 n increases by one the initial arres code written in it. In addition, on the same signal, the synchronizer 2 forks the second call to memory block 5 and the enable signal for the operation of the generator 8 of the symbol sweep. According to the changed code of the initial address and the second address, the code of the second symbol vector is stored at the output of the memory block 5, which is stored in its output register. From the moment the code of the first vector is written into register 7, the sweep generator 8 generates the vector sweep voltages in X and Y coordinates, the illumination unit 9 (L1 determines the beam intensity on the CRT screen, and the b code-time converter specifies the vector length in proportion to the received code. Output signal Coax transducer 6 is the vector end signal. According to the first vector end signal, the code of the start address in counter 4 is increased by one more unit, control block 2 forms the third call to memory block 5, and the second vector code the symbol from memory block 5 is rewritten into register 7 and converter 6 in time, From this point in time, the sweep generator 8 and the backlight unit 9 output the second vector of symbols from the CRT screen in accordance with the program of its construction. of all the other codes of the vectors of the symbol being formed and outputting them to the CRT screen. When forming the last vector of the symbol by the sweep generator 8, the output of the memory block 5 produces a zero number on all bits that defines the end firmware build character. Three bits of this number arrive at the information input of the control unit 2 which, using this code and the last signal of the vector end, generates the signal of the end of the symbol, which sets the device to the zero state and enters the device output 17 to call the next character code from the external control device ( not shown). If it is necessary to form a wave with its second., Characteristic (the upper case symbol changes to a lower case), the character type indicator in the vice signal of a logical unit is fed to the input 16 of the device. By this signal, the trigger 12 is set to one. The unit level from the direct output of the trigger 12 opens the element 11 and the zero level from its inverse output blocks the element 10, the zero level from the output of the element 10 blocks the passage of the initial address of the uppercase character from the block 5 of the memory 5 selected by the first treatment. The recording signal of the initial ASHEES passes through the AND 11 element to the second switching input of the 3 ZI-OR elements block and allows the string of the starting character from the output of the 13 memory block to pass through the 3 n information input of the counter -4. After writing the code of the starting address of the lower-case character to the counter 4, the control unit 2 generates a second call to the memory block 5. By this inversion and the code of the starting address from the output of counter 4, memory block 5 forms the code of the first vector of the line character. The further work of the device on the formation of vector codes and scanning voltages of a lowercase symbol occurs similarly to the formation of an uppercase symbol. Similarly, the device can be used, for example, to form the same character code of the Russian and Latin alphabets, as well as characters that differ in size or configuration. The proposed device provides, without changing the input code, the possibility of forming characters in different ways: with a font (uppercase, lowercase, enlarged and enlarged size) due to the fact that the device has two firmware for the same input code, a symbol: constructions whose starting addresses are placed in two memory blocks, which excludes their dependence on the value of the input code. In the known device, such an opportunity does not exist, since the codes of the national addresses of the generated symbols are located in one memory block according to military law. In this case, each symbol's input code has the corresponding initial error of the initial Aares for this code. You can only select the bottom of the microscript of its construction. The proposed device also provides the ability to change the entire alphabet of generated characters (for example, replace the Russian alphabet with Latin or some other) by inputting only one type of character type to the device input, which can be done by pressing the corresponding button 1 on the operator’s console of the display device replacing some special characters with others in the process of incoming information, which contributes to the reduction of informativeness (obtaining additional characteristics of the output It is possible to expand the area of the PC by forming the symbol of two different alphabets (nomenclature), which makes it possible to use the device in two different information display systems without additional costs. The technical and economic efficiency of the invention consists in expanding the functional capabilities of the device.

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Claims (1)

A DEVICE FOR FORMING SYMBOLS, containing a pulse generator, one of the inputs of which is connected to the first input of the device, the other input to the first output of the device, to the first input of the counter and to the first output of the control unit, the second output of which is connected to the first input of the block of elements ZI-OR the second input of which is connected to the second input of the device, the third input of the block of ZI-OR elements is connected to the output of the first memory block, with the first inputs of the converter the code is time, register and control unit,. the second input of which is connected to the output of the pulse generator, the third input is the output of the converter code is time, the second inputs of the register and counter, the third input of which is connected to the output of the block of elements ZI-OR, the output of the counter is connected to one of the inputs of the first memory block, the other the input of which is connected to the third output of the control unit, the fourth output of which is connected to the second input of the code-time converter, the fifth output is to the first input of the scan generator, the outputs of which are connected to the second and third outputs of the device, the second input of the sweep generator is connected to one of the outputs of the register, the other output of which is connected through the backlight unit to the fourth output of the device, characterized in that, in order to expand the scope of the device by changing the nomenclature and configuration of characters without changing the input code or replacing the memory unit, it contains the second memory block, the trigger, the first and second AND elements, the outputs of the first and second AND elements are connected to the fourth and fifth inputs of the block of elements Z-OR, the sixth input of which is connected to the output m of the second memory block, the inputs of which are connected to the first and second inputs of the device, the third input of the device is connected to one of the inputs of the trigger, the other input of which is connected to the first output of the control unit, the sixth output of which is connected to the first input of the first and second elements AND, the second input which is associated with the outputs of the trigger. \ 0908801