SU943700A1 - Data display device - Google Patents

Description

(54) DEVICE DPJA INFORMATION DISPLAY

Claims (2)

The invention relates to automation and computer technology and can be used in devices for forming symbols on a screen of an electron beam tube (CRT). A device for displaying information is known, comprising a character code register, a symbol memory block, a polling unit, a vector counter, a generator, a microinstructor register, function voltage generators, a beam Modlight block, a converter, and a logical block Cl 3 The lack of a known device is limited (} the adjustment of complex characters consisting of a large number of vectors and the impossibility of forming composite characters consisting of individual characters or their parts.... The closest in technical essence This is a device for displaying information containing a memory block connected to a register, a function voltage generator connected to a register, a code-time converter connected to a pulse generator and a register connected to a beam illuminator, an address counter, a logic block and (| pulse generator connected to a pulse generator, code-time converter, function voltage generator, memory block, address counter and logic block connected to the memory block address counter connected to a time-code converter, and memory block. In this device, each character, regardless of its complexity, is formed by sequential sampling of codes of vectors from the block of frame. In many cases, separate parts of the contours of different symbols may coincide. At the same time, the codes of the same vectors are repeatedly recorded in the memory block, which limits 3 the total number of generated symbols 2. A disadvantage of the known device is the impossibility of forming additional composite symbols from a given set of basic symbols, which limits its scope. The aim of the invention is to expand the scope of application of the device by forming symbols of complex configuration. The goal is achieved by the fact that a known device containing two groups of elements AND, information inputs of the first of which are information inputs of the device, control inputs of elements AND of the first and second groups are connected to the first output of the synchronizer, information inputs of the elements of the second group - to the output of the first the memory block, and the outputs - to the inputs of the elements OR groups, the outputs of which are connected to the first input of the first counter, the second input of which is connected to the second output of the synchronizer, third, quarters The fifth and sixth outputs of which are connected to the first input of the sweep generator, the reset inputs of the pulse generator and the code-time converter, the sync input of the first memory block and the code – time converter clock input, respectively, and the first and second inputs to the outputs of the pulse generator and the code-time converter, respectively, the output of the first counter is connected to the address input of the first memory block, and the output of the time converter is connected to the first register input, the first and second outputs of which are connected to the second input of the generator the scanner and the input of the illumination unit, and the synchronous input of the pulse generator is the synchronous input of the device, additionally containing a second memory block whose synchronous input is connected to the seventh output of the synchronizer, the first one. OUTPUT - to the information input of the code-time converter and the third input of the pulse generator, and the second output - to the second register input, the second counter, the first, second and / third inputs of which are connected to the eighth synchronizer output, the output of the code-time converter and the output of the first memory block. respectively, the output is with the information input of the second memory block and 0.4 element I, the first input of which is connected to the output of the time converter, the second input to the third output of the second memory block, and the output to the third input of the first counter, and the fourth inputs of the synchronizer and second counter. Fig, 1 shows a block diagram of the device; on fin. 2 - type of symbol being formed; in fig. 3 and 4 time diagrams of basic sigma. fishing The device contains a pulse generator 1, a synchronizer 2, the first memory block 3, the first counter C, the first group of elements 5, the code-time converter 6, the register 7, the scan generator 8, the backlight unit 9, the second counter 10, the second memory block 11, the second group of elements AND 12, the element AND 13 group of elements OR N. Positions 15-38 denote the inputs and outputs of the device units. The device works as follows. At the initial time t, synchronization input 1b of the device is triggered by a synchronization pulse, pulse generator 1, which at output 20 forms a burst of clock pulses from the beginning of the synchronization pulse to the appearance of the end-of-symbol signal. The synchronizer 2 at the first output 22 at time t generates a signal for writing the symbol code from the information input 15 of the device to the first counter t (address counter) through the groups. elements 5, 12 and 1Л, and on the fifth output 27 the first interrogation signal of the first memory block 3- According to the symbol code from the output 25 of the first counter and the interrogation signal from the fifth output 27 of the synchronizer 2 at the output 28 of the first memory block 3 time point tr is generated by the first-digit number that determines the code of the starting address of the character's firmware. The symbol firmware consists of two parts and is written into two memory blocks. The first part defining the codes of the initial addresses of the main characters or their individual colors is recorded in the first memory block 3. The second part defining the codes by the main character vector codes, transition codes and end-of-character codes is recorded in the second memory block F. At time ta, synchronizer 2 generates 23 sig- at the second output. Setting the first counter to zero k. At the same time, at the fifth output 27 of the synchronizer 2, a signal is polled from the first memory block 3. At the time 1d, the first output 22 of the synchronizer 2 generates a second recording signal, according to which the code of the initial address from output 28 of the first memory block 3 through the second the group of elements 12 and the group of elements 1 is recorded in the first counter 4; at time t, the fifth output 27 of synchronizer 2 generates a zero output register of the first memory block 3 (not shown) and a second interrogation signal. The starting address code recorded in the first counter and the second interrogation signal from the fifth output 27 of synchronizer 2 at time tt, output 28 of memory 3, forms a second n-bit number that determines the address code of the first vector of the figure 1 of the composite symbol of FIG. 2. At time t, at the eighth output 24 of synchronizer 2, it forms a signal for recording the address code from the output of memory block 3 to the second counter 10 (vector counter). At the same time, at the seventh output 31 of the synchronizer 2, the first interrogation signal of the second memory block 11 is generated. At time t, the first vector of the initial vector figure of the composite symbol is generated at the first and second outputs 33 and 3 of the second memory block 11. In the device, the output number of the second memory block 11 is determined by 11 bits, the 1-6 bits control the operation of the sweep generator 8, of which 1, 2, TsL Zy bits defines respectively the slope of the sawtooth voltages X and Y, and the 3rd and 6th bits are their sign, i.e. the rising or falling portion, the 7th bit determines the backlight of the ZLT beam, the 8-10th bits are designed to control the operation of the code-time converter 6, which determines the length of the generated vector of the symbol. In addition, they are in synchronizer 2 (if there are zeros in all bits) w: they are used to form a signal that all the nodes of the device are set to zero, and the nth digit is intended to select the signals of the end of the original figures or their individual parts. at time tg, the converter i-6 code-time at output 30 generates a signal to start recording the code of the first vector of the symbol in the register of 7 micro-instructions and in the converter 6 in time. At the same time, this signal increases the state of the counter 10 vectors per unit of the least significant bit, and the interrogation signal of the memory block 11 is acquired. From the first and second outputs 35 and 36, respectively, of the register 7 micro-commands, the orientation code of the first vector of the symbol is fed to the information inputs of the scan generator 8 and the backlight unit 9. Simultaneously, from the third output 37, the synchronizer 2 to the first - control input of the generator 8 receives a signal for enabling the operation of the generator of the symbol sweep, under the action of which the generator 8 generates the sweep voltage along the X and Y axes of the first vector of the composite symbol. The length of the formed vector is proportional to the time code received from the first output 33 of the second memory block 11 to the code-time converter 6. The moment of the end of the formation of the vector is fixed by the signal of the end of the vector at the output 30 of the code-time converter 6. At time t, the seventh output 31 of the synchronizer 2 forms a signal that the second memory block 11 is set to zero and a new interrogation signal is generated. From the known code from output 29 of the second counter 10 vectors and the new interrogation signal from the seventh output 3t of synchronizer 2 at time t, the second memory block 11 generates the scan code of the second symbol vector, which is stored in its output register. At time t, the code-time converter 6 at output 30 generates a signal for the end of the first vector of the composite symbol, according to which the code of the second vector from 4 wave from the second memory block 11 is rewritten into micro-command register 7 and the code-time converter 6. At the same time, with the same signal, the code at output 29 of the BTOporot counter of 10 vectors increases by one more unit of the least significant bit and the polling signal at output 31 of synchronizer 2 is removed. From this point in time, generator 8 generates a second vector sweep signal, and code-time converter 6 determines its length. All-subsequent vectors constituting the contour of the first source figure of the symbol are formed in a similar way. At time t, a signal of a logical unit is received at the third output 32 of the second memory block 11, arriving at the second input of the element 13. At the time point at the output 26 of the element 13, the signal of the end of the third vector of the first figure of the symbol is extracted. According to this signal, the code at the output 25 of the first counter, k, is incremented by one unit of the least significant bit, and the second counter, 10, is set to zero. At the same time, at the fifth output 27 of the synchronizer 2, the next interrogation signals are generated and the first memory block 3 is set to zero. At the time output 28 of the first memory block 3, the address code of the first vector of the second composite symbol is generated, which by the signal from the eighth output 2k of synchronizer 2 is rewritten to the second counter 10 at the moment of time. Simultaneously, at the seventh output 31 of the synchronizer 2, the next polling signals of the second memory block 11 are generated. At the time 1. at the outputs and 33 of the second block pa tee 11 is formed of the first code vector of the second figure composite character which, after completion of the last vector generating first figure composite symbol at time pe-. Writes to code-time transducer 6 and micro-command register 7. From this point in time, the formation of the vectors of the second figure of the composite symbol begins similarly to the first. At the time point, at outputs 3 and 33 of the second memory block 11, an output number is generated containing zeroes in all bits. Three bits of this number from output 33 arrive at the third input of synchronizer 2, which, by the signal of the end of the last vector of the second figure at time tj, forms the signal of the end of the symbol. This signal from the fourth output 3 of the synchronizer 2 sets all the nodes of the device to zero and simultaneously arrives at the output 17 of the device to call the next character code from an external control device (shown). Similarly, any other composite symbol can be formed from other simple symbols that have their own application, as well as from separate parts of different symbols. Or specially pre-appointed for this figures. Thus, the application of the proposed device has the positive effect that the device allows the formation of an additional number of new co. fixed characters from a set of simple characters that have their own application. In this case, the information volume of the memory blocks is used more efficiently, and the compilation of microprograms of symbols is simplified. An apparatus for displaying information containing two groups of elements AND, information inputs of the first of which are information inputs of the device, control inputs of elements AND of the first and second groups are connected to the first output of the synchronizer, information inputs of elements of the second group are to the output of the first the memory block, and the outputs - to the inputs of the elements OR groups, the outputs of which are connected to the first input of the first counter, the second input of which is connected to the second output of the synchronizer, third, quarter The fifth, fifth, and sixth outputs of which are connected to the first input of the sweep generator, the reset inputs of the pulse generator and the code-time converter, the synchronous input of the first memory block and the synchronous input of the code-time converter, respectively, and the first and second inputs to the i outputs of the pulse generator and the code-time converter, respectively, the output of the first counter is connected with the address input of the first memory block, and the code-time converter output with the first register input, the first and second outputs of which are connected to the second input of the gene The scanner and the input of the illumination unit, and the synchronous input of the pulse generator is a synchronous input of the device, characterized in that, in order to expand the field of application of the device due to the formation of symbols of complex configuration, it contains a second memory block, the synchronous input of which is connected to the seventh synchronizer output , the first output is to the information input of the code-time converter and the third input of the synchronizer, and the second output to the second input of the register, the second counter, the first second and third inputs of which are connected to the eighth output of the synchronizer I output of the code-time converter and the output of the first memory block, respectively, and the output with the information input of the second memory block and E O element I, the first input of which is connected to the output of the time converter, the second input to the third output of the second memory block, and the output to the third input of the first counter, and the fourth. inputs of the synchronizer and the second counter. Sources of information taken into account in the examination 1. USSR author's certificate number, cl. G06 K 15/20, 1973. 2. USSR author's certificate tf, cl. G06 K 15/20, 1976 (prototype). I f.t., G-