SU1441451A1 - Device for displaying information - Google Patents

Abstract

The invention relates to computing and automation and can be used to display alphanumeric and graphic information on the screen of a television video monitoring device in information-measuring and computing systems. The purpose of the invention is improving the speed of the device. The device contains a generator of 1 clock frequency, a counter of 2 points, a counter of 3 characters, a counter of 4 raster lines, a counter of 5 information lines, shapers 6 and 7 lowercase and frame sync pulses, a decoder 8, first 9 and second 10 address multiplexers, first 11 and second 12 blocks memory, character generator 13, shift register 14, key 15 and control unit 16 with corresponding links. The increase in speed is achieved due to the fact that the information on the contents of the character string is stored in the first RAM block I1, and the information about the order of the character rows in the second RAM block 12. In this case, the content of the repeated 3HaKOBf ix lines is written into the first memory block 11 once. 1 il. F (L 4 4 1 sd

Description

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The invention relates to automation and computing and can be used to display alphanumeric and graphical information on the screen of a television video monitoring device in information-measuring and computing systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows a block diagram of the proposed device.

The device contains 1 clock frequency generator, 2 point counter, 3 character counter, 4 raster line counter, 5 information lines counter, 6 horizontal sync shaper, 7 frame sync shaper, decoder 8, first address multiplexer 9, second address multiplexer 10, first block

11 operative memory, second block

12 memory, character generator 13, shift register 14, key 15 and control unit 16.

The device works as follows.

The device forms an image on the screen of a television video monitoring device (TLV) as a sequence of information lines. The set of displayed characters is specified by the character generator 13.

Each information line displayed on the screen corresponds to a certain area of the first block of 11 operational taps, equal in volume to the number of signals displayed in the information line.

The code of the signal recorded in the first memory block 11 is applied to the higher address bits of the character generator 13 and selects the area where the codes of the segments of the displayed sign are recorded. The selection of the currently displayed character segment is made by the output code of the 4-bit-line counter, applied to the lower bits.

addresses of the character generator 13.

Converting the sign segment into a serial code necessary to form a video signal is produced by the shift register 14, the writing of the output code of the PZ character generator 13 into the shift register 14 is controlled and its sequential shift is performed by the decoder 8, which

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This in turn is controlled by the outputs of the 2 point counter.

The selection of the code of the displayed character of the information line is made by setting the lower address bits, and the selection of the displayed lines is set by the higher address bits of the first RAM block 11. The address of the displayed character is generated by a 3-character counter and is fed to the address inputs of the first RAM block 11 via the first address multiplexer 9.

The high-order code of the first RAM block 11, representing the code of the displayed memory line, is read from the second RAM block 12. The output code of the counter 5 information lines, which is fed to the address input of the second RAM block 12 through the second address multiplexer 10, is used as the address code of the second RAM 12. In the second RAM block 12, a pre-record of the lines of memory strings is displayed, which are displayed on the screen in the required sequence and combination.

The device works in two modes: c. image regeneration mode and information input mode.

In the regeneration mode, the operation of the first memory unit II, the second memory unit 12, the character generator 13 and the decoder 8 is controlled by a clock frequency generator 1 and counters 2-5. The division factor of the 2 point counter determines the number of elements in the sign segment, The conversion factor of the 3-character counter is equal to the number of characters in the information line, the 4-bit line counter determines the number of segments in the generated character, and counter 5 - the number of information lines in the image, At p In the image regeneration mode, the first multiplexer 9 of the address switches the output signals of the 3-character counter and the second block 12 of the operational memory to the address inputs of the first RAM block I1, the second multiplexer 10 of the address switches the output signals of the 5 information lines to the address inputs of the second RAM 12 block . Wherein

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The first 9 and second 10 address multiplexers are controlled by a signal from the second output of the control unit 16. The first 11 and second 12 blocks of RAM, controlled respectively by signals from the third and fourth outputs of the control block 16, are in the information reading mode. The key 15, controlled by the first output of the control device, is closed. The formers of 6 and 7 lowercase and frame sync pulses generate synchronization signals for the sweep generators.

In the information input mode, information is recorded in the first RAM block 11 and in the second RAM block 12. Address

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These, and the order in which the character is located, the lines on the screen are specified by the contents of the second RAM block 12.

Claims (1)

Invention Formula A device for displaying information comprising a clock generator, a point counter, a character counter, a raster line counter, an information line counter, a horizontal sync driver, a frame sync driver, a decoder, the first address multiplexer, the first block of RAM, character generator, shift register, control whose inputs are connected to the outputs of the decoder. memory cells through which 2o inputs are connected to the first the outputs of the point counter, the counting input of which is connected to the output of the clock frequency generator, the second output of the point counter is connected to the clock input of the character counter, the first output of which is connected to the com input of the counter of raster lines, the first output of which is connected to the clock input of the information line counter, the first the output of which is connected to the input of a frame sync pulse generator, the output of which is the first sync device of the device, the second sync input of which is the output of a horizontal sync pattern pulses, the input of which is connected to the second output of the character counter, the third output of which is connected to the first information input of the address multiplexer, the output of which is connected to the address input of the first RAM block, the output of which is connected to the first address input of the cogenerator, the output of which is connected to the information input of the shift register, the second address input of the character generator is connected to the second output of the raster row counter, the information input of the first RAM block is connected to the output row key, a control input of which is connected to the first output of the control unit, the second output of which is connected to the control input of the first multiplexer the first address, the second yn formational input of which is an address input unit, the control input of which is recording information from the external bus of the device address, through the first 9 and second 10 multiplexers of the address is fed to the address inputs of the first 1 and second 12 blocks of RAM. Recorded information is fed to the information inputs of the ram blocks 11 and 12 from the external data bus of the device through a switch 15, the operating modes are controlled by the control blocks 16, the output signals of which synchronize the recording of information into the ram blocks 11 and 12 are switching information of the first 9 and second 10 address multiplexers, as well as a key 15. The initial information for operation of the control unit 16 comes from the external control bus of the device. In the information input mode, an active signal is generated at the first and second outputs of the control unit 16, switching the first 9 and second 10 multiplexers to pass signals from the external address bus of the device to the address inputs of the corresponding blocks 11 and 12 and open the key 15, Recording information on the set address is produced by the device control bus signal. The use of the proposed device provides an increase in speed when editing and generating images due to the fact that the repeated character lines of the image are encoded once in the first operative memory block 11, the inputs of which are connected to the first 5 o five 0 five 0 five the outputs of the point counter, the counting input of which is connected to the output of the clock frequency generator, the second output of the point counter is connected to the clock input of the character counter, the first output of which is connected to the clock input of the counter of raster lines, the first output of which is connected to the clock input of the counter of information lines, the first output of which connected to the input of the frame sync pulse generator, the output of which is the first sync device of the device, the second synchronized input of which is the output of the horizontal sync generator pulses, the input of which is connected to the second output of the character counter, the third output of which is connected to the first information input of the address multiplexer, the output of which is connected to the address input of the first RAM block whose output is connected to the first address input of the character generator whose output is connected to the information input the shift register, the second address input of the character generator is connected to the second output of the raster row counter, the information input of the first RAM memory block the exit key, the control input of which is connected to the first output of the control unit, the second output of which is connected to the control input of the first address multiplexer, the second information input is an address input unit, the control input of which is the input of the control unit, the third output of which is connected to the control input of the first memory block, the information input of the key is the information input of the device, the video output of which is the output of the shift register, characterized in that it contains the second multiplexer addresses and a second memory block whose address input is connected to the output of the second multiplexer of the address, the first information input of which is connected to the second output the information line counter, the second information input of the second multiplexer of the address is connected to the address input of the device, the control input of the second multiplexer of the address is connected to the second output of the control unit, the fourth output of which is connected to the control input of the second RAM block, the output of which is connected to the third the information input of the first multiplexer of the address, and the information input of the second RAM block is connected to the output of the buffer element.