SU1689983A1 - Crt display unit - Google Patents

Abstract

The invention relates to automation and computer technology and is intended for use in raster indicators on a cathode ray tube. The purpose of the invention, an increase in the information capacity of the device, is achieved by recording information about the sign into register 1, from which the sign code goes to one of the inputs of the block 3 of the permanent character memory, the Y coordinate to the inputs of the adder 2, the lower bits of the X coordinate - to the inputs of blocks 12 and 13 of the permanent memory, the high bits of the X coordinate to the switch 4. Counter 10 counts up to nine (the number of lines in the sign). The signals from the outputs of the counter 10 are fed to the second inputs of the adder 2 and added to the Y coordinate. The total code on the Y coordinate and the higher bits of the X coordinate are the address to write

Description

Fig. /

in block 5 of the raster memory, the read address is generated by the read address shaper 8. Permanent memory unit 3 generates the position code of the character string, which is fed to one of the inputs of the permanent memory unit, the other inputs of which receive the least significant bits of the X coordinate, which determine the position of the seven points of the character string within 16 points raster. The signals from the outputs of block 12 of the permanent memory are fed to the information inputs of block 5 of raster memory. The video signal for each character is generated by the shaper 6. All work is synchronized and controlled by the synchronizer 7. beat.

The invention relates to automation and computer technology and is intended for use in raster indicators on a cathode ray tube,

The purpose of the invention is to increase the information capacity of the device.

FIG. 1 shows a functional diagram of the device; figure 2 - oscillogram of the output signals of the synchronizer; FIG. 3 is a functional diagram of a synchronizer; Fig. 4 is a functional block diagram of the raster memory; Fig. 5 is a functional block diagram of a fixed memory chip selector; Fig. 6 is a functional block diagram of the data storage unit.

The device contains a register 1, an adder 2, the first permanent memory unit 3, a switch 4, a raster memory unit 5, a video signal forming unit 6, a synchronizer 7, a read address generator 8, a trigger 9, an estimator 10, element 11, the second 12 and third 13 blocks of permanent memory,

Synchronizer 7 contains a generator of 14 clock cycles, the first 15 second 16, third 17 and fourth 18 binary counters, a decoder 19, shapers 20-25 pulses.

Block 5 of the raster memory contains the group of elements OR 26, the matrix 27 of the rectifier and the reader.

The block 12 of the permanent memory contains the element NOT 28 and the matrix 29. of the drives.

Block 13 of the permanent memory contains the element HE 30 and the matrix 31 of the drives.

The device for displaying information on the screen of the cathode-ray tube operates in two modes: in the write mode in the raster memory unit 5 and in the read mode from the raster memory unit 5. The CAPACITY of the raster memory block 5 is chosen equal to the number of decomposition points of the indicator's television raster, i.e. Each raster point has its own memory cell in raster memory block 5. The writing of the points of the sign in block 5, as well as the reading, is carried out synchronously to the horizontal scan, and the writing and reading are carried out by pulses, the repetition period of which is equal to 16 periods of the pulses of the points of the line of the television raster. One pulse writes the entire string or a part of the character string, and 16 points of the raster string are read simultaneously.

To write the characters into the raster memory block 5, information arrives at the device input (the sign code and the X and Y coordinate code of the sign position on the indicator screen). The information is written to register 1 by pulse recording. Register 1 is made on two-stage, synchronous, dynamic D-triggers. One D-trigger is used in each register bit. The entire operation of the device is controlled by the synchronizer 7, which produces pulses of line points (Fig. 2a), pulses (Fig. 2 g, d), controlling the operation of block 5 of the raster memory, pulses (Fig, 2c), controlling the operation of block 12 data memory and constant memory unit 13 (chip select), pulses (Fig. 2b) controlling the operation of the switch 4 (addresses), pulses (Fig. 2e) controlling the operation of the video signal generator 6, horizontal scanning pulses SHI (fig, 2z) and pulses of the frame sweep of the OIG (fig.2).

In the synchronizer to ensure high stability of the frequency of the pulse points, the generator 14 is made using a quartz resonator. Frequency division is performed by binary counters 15-18, which are performed on two-stage triggers and provide frequency division by 16.

A decoder 19 and shapers 20-25 pulses are used to form the pulses (Fig. 2 b, d, c, d, e). Each driver is built on logical elements 2 AND-NOT, 3 AND-NOT, 4 AND-NOT and dynamic triggers D.

An input pulse arriving at the input to the S input of trigger 9 sets it to one state. The inverse output of the trigger 9 is the installation input of the counter 10 (character string). The counting input of the counter 10 from the output of the synchronizer 7 receives pulses (figv). Counter 10 is a binary counter, the width of which is determined by the number of character lines. With a character size of 7x9 (seven raster elements per line and nine raster elements per frame), the counter size 10 must be equal to four. Since the counter 10 must count to nine, then to reset it to the zero state, the 11th pulse on the element 11 selects the ninth row pulse that arrives at the R input of the trigger 9, sets its inverse output to one state, thereby setting counter 10 to zero.

The code from the output of the counter 10 is fed to the second address inputs of the block 3 of the permanent memory of characters. At the information inputs of block 3 from register 1 comes the sign code. In accordance with the character code for each line, block 3 generates a positional seven-digit code of character points in the line. Block 3 of the permanent character storage is a programmable permanent memory switch PROM. The first four bits are used for the character string code, the second seven bits are for the character code.

From the output of block 3 of constant memory of characters, the positional seven-digit code of character points in the line goes to the second address inputs of block 12 of constant data memory, to the first address inputs from outputs of lower bits of the X coordinate of register 1 enters a four-bit code of lower bits X coordinates. A constant data storage unit 12 forms a positional sixteen-bit data code, consisting of a positional seven-bit code of character points in a line, shifted within sixteen points, and nine insignificant bits. The constant memory unit 12 is a matrix switch with a field of 7x16, which allows to transmit seven input signals to any seven of the sixteen outputs, provided that no more than one input is connected to each output. The connection between the input and the output determines the four-bit code of the lower bits of the X coordinate. Block 12 of the permanent memory contains the element NOT and a programmable permanent memory of the EPROM, the capacity of which is determined by the positional seven-digit character code points in the line and four-digit the bottom code of the least significant bits of the X coordinate. At the output of block 12, we obtain the position sixteen bit code

data that enters the information inputs of the raster memory block 5

The fixed memory (chip select) unit 13 forms a positional sixteen-bit chip select code for the raster memory block 5 when writing a character string to it.

The code from the output of the counter 10 is fed to the second inputs of the adder 2, the first inputs of which from the outputs of register 1 receive the coordinate code Y of the beginning of the character. Adder 2 is a ten-bit binary combiner adder. The summary code of the Y coordinate is fed to the second information inputs of the switch 4, the first information inputs of which register the highest bits of the X coordinate from the register, together they are the address for block 5 of raster memory when writing character strings to it.

The address for reading information from the raster memory block 5 is generated by the read address generator 8, which contains a binary pulse counter in the raster row and a binary raster row counter. In order to set the counters to the zero state, MMI pulses are sent to the setup inputs from the synchronizer 7. The counting pulses of the pulse counter in a raster row are pulses (Fig. 2b), the counting pulses of the row counter are SGS. The outputs of the pulse counter in the raster line are the read address of the X coordinate, the outputs of the raster line counter are the read address of the Y coordinate.

The signal from the outputs of the imaging unit 8 is supplied to the third information inputs of the switch 4, which is controlled by a pulse (Fig. 26). In the positive phase of the pulse (Fig. 2b), the switch output passes the address from the driver 8 to read information from block 5, and in the negative phase of the pulse (Fig. 26), the address from the register 1 and the adder 2 passes the switch output to the information block 5 raster memory. Switch 4 provides address switching from two directions to one.

The raster memory block 5 (Fig. 4) contains sixteen OR elements 26 and a drive matrix 27 with a capacity corresponding to the number of raster decomposition elements. A signal is supplied to the first inputs of the OR element 26 (Fig. 2d). The signal (Fig. 2e) is controlled by a raster memory block 5. When reading information, the second inputs of the OR 26 element receive signals from the output of block 13. These signals

Select seven raster memory chips from 16 when writing a character string to it.

The read information about the 16 points from the output of the raster memory block 5 is fed to the video signal shaper 6, to the control input of which a signal arrives from the synchronizer 7 (Fig. 2e). Shaper 6 converts parallel information about 16 raster points into a serial one and contains a shift register with serially parallel input / output of information and a cable amplifier. The incoming information on the 16 points on the cutoff of the signal (Fig. 2e) is written to the register. The information is shifted by pulses of line points (Fig. 2a). Consistently read information is fed to the cable amplifier of the driver 6, and from the output of the cable amplifier to the output of the device.

The invention allows to increase the amount of information displayed by reducing the time for writing one character to the raster memory,

Claims (1)

An apparatus for displaying information on a cathode-ray tube (CRT) screen containing a register, whose information inputs are device information inputs, and a control input / signal input device record, the outputs of the first register group are connected to the information inputs of the first switch group, information inputs of the second group of which are connected to the outputs of the adder, and information inputs of the third group - to the outputs of the read address generator, whose control input is connected It is connected to the first output of the synchronizer connected to the counting input of the read address generator, the outputs of the second register group are connected to the inputs of the first group of the adder, the outputs of the third register group are connected to the address inputs of the first memory block, the switch outputs are connected to the address inputs of the raster memory block The outputs of which are connected to the information inputs of the video signal generator, the output of which is the output of the device for connection to the CRT modulator, the second and third outputs will synchronize ora are connected to the control inputs of the raster memory block, the fourth and fifth outputs of the synchronizer are connected to the control inputs of the video shaper, and the sixth and seventh outputs are connected to the control inputs of the read address generator, and are outputs of the device for connection to a CRT deflection system, a counter and an AND element, characterized in that, in order to increase information capacity of the device, it contains a trigger, the S input of which is connected to the signal input of the device Record, the output is connected to the installation input of the counter, the outputs of the counter are connected to the inputs of the second group tyMMaTopa, the control inputs of the first permanent memory unit, and the inputs of the And, the output of which is connected to the R-input of the trigger, the counting input of the counter is connected to the eighth output the synchronizer, the second and third blocks of permanent memory, the control inputs of which are connected to the eighth output of the synchronizer, the outputs of the second block of permanent memory are connected to the information inputs of the raster memory block, the inputs of the sampling control of which are connected to the outputs of the third block of permanent memory whose address inputs and address inputs of the first group are connected to the outputs of the fourth group, the outputs of the first block of permanent memory are connected to the address inputs of the second group of the second block of permanent memory. 1699983  J V f «7 I 9« a # I «2 $ H f e i $ Y b) llliiiii1lliishish1 6) (L IGYASCH f- i-- | r- ЈГ 75 y) -y y // V ff cAJL g L-jT. four) FIG. 2 . 3 75 / SGBV KGC OIG SGC but it is countable (lines of the sign on the nag upra & bcho bho & and block los / r of the multiple memory Ay # yta on the ojtoca permanent panel of the choice of str0l4 & ChPra & l Yushn & od yummut- - irtooff actoecv and sufm / # & o0 , chmOn the wpeca read but control inputs raster memory / on controllers / formro & sgt & FIG. four From 1 $ 0 oo MAfffa rsguMob 5X0PtfOtO jaotMfi fr and / thresholds otf- mda (cfm # r p0 / X and V | S one four one “§ Phage. b